2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2002,2003, Motorola Inc.
4 * Xianghua Xiao <X.Xiao@motorola.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <ppc_asm.tmpl>
27 #include <asm/cache.h>
41 /* TLB1 entries configuration: */
43 .section .bootpg, "ax"
48 /* Number of entries in the following table */
51 .long TLB1_MAS0(1,1,0)
52 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
53 .long TLB1_MAS2(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
54 .long TLB1_MAS3(((CFG_CCSRBAR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
56 #if defined(CFG_FLASH_PORT_WIDTH_16)
57 .long TLB1_MAS0(1,2,0)
58 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
59 .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
60 .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
62 .long TLB1_MAS0(1,3,0)
63 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_4M)
64 .long TLB1_MAS2((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,1,0,1,0)
65 .long TLB1_MAS3((((CFG_FLASH_BASE+0x400000)>>12)&0xfffff),0,0,0,0,0,1,0,1,0,1)
67 .long TLB1_MAS0(1,2,0)
68 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16M)
69 .long TLB1_MAS2(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
70 .long TLB1_MAS3(((CFG_FLASH_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
72 .long TLB1_MAS0(1,3,0)
73 .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
74 .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
75 .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
78 #if !defined(CONFIG_SPD_EEPROM)
79 .long TLB1_MAS0(1,4,0)
80 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
81 .long TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
82 .long TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
84 .long TLB1_MAS0(1,5,0)
85 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
86 .long TLB1_MAS2((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,0,0,0)
87 .long TLB1_MAS3((((CFG_DDR_SDRAM_BASE+0x4000000)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
89 .long TLB1_MAS0(1,4,0)
90 .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
91 .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
92 .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
94 .long TLB1_MAS0(1,5,0)
95 .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
96 .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
97 .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
100 .long TLB1_MAS0(1,6,0)
101 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_64M)
102 #if defined(CONFIG_RAM_AS_FLASH)
103 .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
105 .long TLB1_MAS2(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0)
107 .long TLB1_MAS3(((CFG_LBC_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
109 .long TLB1_MAS0(1,7,0)
110 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
111 #ifdef CONFIG_L2_INIT_RAM
112 .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,1,0,0,0,0)
114 .long TLB1_MAS2(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,0,0,0)
116 .long TLB1_MAS3(((CFG_INIT_RAM_ADDR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
118 .long TLB1_MAS0(1,8,0)
119 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
120 .long TLB1_MAS2(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
121 .long TLB1_MAS3(((CFG_PCI1_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
123 .long TLB1_MAS0(1,9,0)
124 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_16K)
125 .long TLB1_MAS2(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,1,0,1,0)
126 .long TLB1_MAS3(((CFG_BCSR>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
129 * RapidIO MMU for 512M
130 * Two entries, 10 and 11
132 .long TLB1_MAS0(1,10,0)
133 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
134 .long TLB1_MAS2(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,1,0,1,0)
135 .long TLB1_MAS3(((CFG_RIO_MEM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
137 .long TLB1_MAS0(1,11,0)
138 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_256M)
139 .long TLB1_MAS2(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,1,0,1,0)
140 .long TLB1_MAS3(((CFG_RIO_MEM_BASE+0x10000000>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
143 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
144 .long TLB1_MAS0(1,15,0)
145 .long TLB1_MAS1(1,1,0,0,BOOKE_PAGESZ_1M)
146 .long TLB1_MAS2(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,1,0,1,0)
147 .long TLB1_MAS3(((CFG_CCSRBAR_DEFAULT>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)
149 .long TLB1_MAS0(1,15,0)
150 .long TLB1_MAS1(0,0,0,0,BOOKE_PAGESZ_1M)
151 .long TLB1_MAS2(0,0,0,0,0,0,0,0,0)
152 .long TLB1_MAS3(0,0,0,0,0,0,1,0,1,0,1)
157 * LAW(Local Access Window) configuration:
159 * 0x0000_0000 0x7fff_ffff DDR 2G
160 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
161 * 0xc000_0000 0xdfff_ffff RapidIO 512M
162 * 0xe000_0000 0xe000_ffff CCSR 1M
163 * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
164 * 0xf000_0000 0xf7ff_ffff SDRAM 128M
165 * 0xf800_0000 0xf80f_ffff BCSR 1M
166 * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M
169 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
170 * If flash is 8M at default position (last 8M), no LAW needed.
173 #if !defined(CONFIG_SPD_EEPROM)
174 #define LAWBAR0 ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff)
175 #define LAWAR0 (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M))
178 #define LAWAR0 ((LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
181 #define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
182 #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_512M))
185 * This is not so much the SDRAM map as it is the whole localbus map.
187 #if !defined(CONFIG_RAM_AS_FLASH)
188 #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff)
189 #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
192 #define LAWAR2 ((LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_128M)) & ~LAWAR_EN)
195 #define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff)
196 #define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M))
199 * Rapid IO at 0xc000_0000 for 512 M
201 #define LAWBAR4 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
202 #define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
205 .section .bootpg, "ax"
210 .long LAWBAR0,LAWAR0,LAWBAR1,LAWAR1,LAWBAR2,LAWAR2,LAWBAR3,LAWAR3