2 * (C) Copyright 2002,2003, Motorola Inc.
3 * Xianghua Xiao, (X.Xiao@motorola.com)
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 extern long int spd_sdram (void);
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
34 long int fixed_sdram (void);
36 #if defined(CONFIG_DDR_ECC)
39 int dma_xfer(void *dest, uint count, void *src);
43 /* MPC8540ADS Board Status & Control Registers */
45 typedef struct bscr_ {
57 int board_early_init_f (void)
59 #if defined(CONFIG_PCI)
60 volatile immap_t *immr = (immap_t *)CFG_IMMR;
61 volatile ccsr_pcix_t *pci = &immr->im_pcix;
63 pci->peer &= 0xffffffdf; /* disable master abort */
75 long int initdram (int board_type)
78 extern long spd_sdram (void);
79 volatile immap_t *immap = (immap_t *)CFG_IMMR;
80 #if !defined(CONFIG_RAM_AS_FLASH)
81 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
85 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
86 volatile ccsr_gur_t *gur= &immap->im_gur;
89 #if defined(CONFIG_DDR_DLL)
92 /* Work around to stabilize DDR DLL */
93 temp_ddrdll = gur->ddrdllcr;
94 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
95 asm("sync;isync;msync");
98 #if defined(CONFIG_SPD_EEPROM)
99 dram_size = spd_sdram ();
101 dram_size = fixed_sdram ();
104 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
105 get_sys_info(&sysinfo);
106 /* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
107 if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
108 lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
110 uint pvr = get_pvr();
112 if (pvr == PVR_85xx_REV1) {
114 * Need change CLKDIV before enable DLL.
115 * Default CLKDIV is 8, change it to 4
118 lbc->lcrr = 0x10000004;
120 lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
122 temp_lbcdll = gur->lbcdllcr;
123 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
124 asm("sync;isync;msync");
126 lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
127 lbc->br2 = CFG_BR2_PRELIM;
128 lbc->lbcr = CFG_LBC_LBCR;
129 lbc->lsdmr = CFG_LBC_LSDMR_1;
131 (unsigned int) * (ulong *)0 = 0x000000ff;
132 lbc->lsdmr = CFG_LBC_LSDMR_2;
134 (unsigned int) * (ulong *)0 = 0x000000ff;
135 lbc->lsdmr = CFG_LBC_LSDMR_3;
137 (unsigned int) * (ulong *)0 = 0x000000ff;
138 lbc->lsdmr = CFG_LBC_LSDMR_4;
140 (unsigned int) * (ulong *)0 = 0x000000ff;
141 lbc->lsdmr = CFG_LBC_LSDMR_5;
143 lbc->lsrt = CFG_LBC_LSRT;
145 lbc->mrtpr = CFG_LBC_MRTPR;
149 #if defined(CONFIG_DDR_ECC)
151 /* Initialize all of memory for ECC, then
155 volatile immap_t *immap = (immap_t *)CFG_IMMR;
156 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
158 for (*p = 0; p < (uint *)(8 * 1024); p++) {
159 if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
160 *p = (unsigned int)0xdeadbeef;
161 if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
165 dma_xfer((uint *)0x2000,0x2000,(uint *)0);
167 dma_xfer((uint *)0x4000,0x4000,(uint *)0);
169 dma_xfer((uint *)0x8000,0x8000,(uint *)0);
171 dma_xfer((uint *)0x10000,0x10000,(uint *)0);
173 dma_xfer((uint *)0x20000,0x20000,(uint *)0);
175 dma_xfer((uint *)0x40000,0x40000,(uint *)0);
177 dma_xfer((uint *)0x80000,0x80000,(uint *)0);
179 dma_xfer((uint *)0x100000,0x100000,(uint *)0);
181 dma_xfer((uint *)0x200000,0x200000,(uint *)0);
183 dma_xfer((uint *)0x400000,0x400000,(uint *)0);
185 for (i = 1; i < dram_size / 0x800000; i++) {
186 dma_xfer((uint *)(0x800000*i),0x800000,(uint *)0);
189 /* Enable errors for ECC */
190 ddr->err_disable = 0x00000000;
191 asm("sync;isync;msync");
199 #if defined(CFG_DRAM_TEST)
202 uint *pstart = (uint *) CFG_MEMTEST_START;
203 uint *pend = (uint *) CFG_MEMTEST_END;
206 printf("SDRAM test phase 1:\n");
207 for (p = pstart; p < pend; p++)
210 for (p = pstart; p < pend; p++) {
211 if (*p != 0xaaaaaaaa) {
212 printf ("SDRAM test fails at: %08x\n", (uint) p);
217 printf("SDRAM test phase 2:\n");
218 for (p = pstart; p < pend; p++)
221 for (p = pstart; p < pend; p++) {
222 if (*p != 0x55555555) {
223 printf ("SDRAM test fails at: %08x\n", (uint) p);
228 printf("SDRAM test passed.\n");
234 #if !defined(CONFIG_SPD_EEPROM)
235 /*************************************************************************
236 * fixed sdram init -- doesn't use serial presence detect.
237 ************************************************************************/
238 long int fixed_sdram (void)
241 volatile immap_t *immap = (immap_t *)CFG_IMMR;
242 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
244 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
245 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
246 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
247 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
248 ddr->sdram_mode = CFG_DDR_MODE;
249 ddr->sdram_interval = CFG_DDR_INTERVAL;
250 #if defined (CONFIG_DDR_ECC)
251 ddr->err_disable = 0x0000000D;
252 ddr->err_sbe = 0x00ff0000;
254 asm("sync;isync;msync");
256 #if defined (CONFIG_DDR_ECC)
257 /* Enable ECC checking */
258 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
260 ddr->sdram_cfg = CFG_DDR_CONTROL;
262 asm("sync; isync; msync");
265 return (CFG_SDRAM_SIZE * 1024 * 1024);
267 #endif /* !defined(CONFIG_SPD_EEPROM) */