2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2002,2003, Motorola Inc.
4 * Xianghua Xiao, (X.Xiao@motorola.com)
6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <asm/processor.h>
31 #include <asm/immap_85xx.h>
34 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
35 extern void ddr_enable_ecc(unsigned int dram_size);
38 extern long int spd_sdram(void);
40 void local_bus_init(void);
41 void sdram_init(void);
42 long int fixed_sdram(void);
45 int board_early_init_f (void)
55 printf(" PCI1: 32 bit, %d MHz (compiled)\n",
56 CONFIG_SYS_CLK_FREQ / 1000000);
58 printf(" PCI1: disabled\n");
62 * Initialize local bus.
71 initdram(int board_type)
74 extern long spd_sdram (void);
75 volatile immap_t *immap = (immap_t *)CFG_IMMR;
77 puts("Initializing\n");
79 #if defined(CONFIG_DDR_DLL)
81 volatile ccsr_gur_t *gur= &immap->im_gur;
85 * Work around to stabilize DDR DLL
87 temp_ddrdll = gur->ddrdllcr;
88 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
89 asm("sync;isync;msync");
93 #if defined(CONFIG_SPD_EEPROM)
94 dram_size = spd_sdram ();
96 dram_size = fixed_sdram ();
99 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
101 * Initialize and enable DDR ECC.
103 ddr_enable_ecc(dram_size);
117 * Initialize Local Bus
123 volatile immap_t *immap = (immap_t *)CFG_IMMR;
124 volatile ccsr_gur_t *gur = &immap->im_gur;
125 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
133 * Fix Local Bus clock glitch when DLL is enabled.
135 * If localbus freq is < 66Mhz, DLL bypass mode must be used.
136 * If localbus freq is > 133Mhz, DLL can be safely enabled.
137 * Between 66 and 133, the DLL is enabled with an override workaround.
140 get_sys_info(&sysinfo);
141 clkdiv = lbc->lcrr & 0x0f;
142 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
145 lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */
147 } else if (lbc_hz >= 133) {
148 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
152 * On REV1 boards, need to change CLKDIV before enable DLL.
153 * Default CLKDIV is 8, change it to 4 temporarily.
155 uint pvr = get_pvr();
156 uint temp_lbcdll = 0;
158 if (pvr == PVR_85xx_REV1) {
159 /* FIXME: Justify the high bit here. */
160 lbc->lcrr = 0x10000004;
163 lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
167 * Sample LBC DLL ctrl reg, upshift it to set the
170 temp_lbcdll = gur->lbcdllcr;
171 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
172 asm("sync;isync;msync");
178 * Initialize SDRAM memory on the Local Bus.
184 volatile immap_t *immap = (immap_t *)CFG_IMMR;
185 volatile ccsr_lbc_t *lbc= &immap->im_lbc;
186 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
189 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
192 * Setup SDRAM Base and Option Registers
194 lbc->or2 = CFG_OR2_PRELIM;
195 lbc->br2 = CFG_BR2_PRELIM;
196 lbc->lbcr = CFG_LBC_LBCR;
199 lbc->lsrt = CFG_LBC_LSRT;
200 lbc->mrtpr = CFG_LBC_MRTPR;
204 * Configure the SDRAM controller.
206 lbc->lsdmr = CFG_LBC_LSDMR_1;
209 ppcDcbf((unsigned long) sdram_addr);
212 lbc->lsdmr = CFG_LBC_LSDMR_2;
215 ppcDcbf((unsigned long) sdram_addr);
218 lbc->lsdmr = CFG_LBC_LSDMR_3;
221 ppcDcbf((unsigned long) sdram_addr);
224 lbc->lsdmr = CFG_LBC_LSDMR_4;
227 ppcDcbf((unsigned long) sdram_addr);
230 lbc->lsdmr = CFG_LBC_LSDMR_5;
233 ppcDcbf((unsigned long) sdram_addr);
238 #if defined(CFG_DRAM_TEST)
241 uint *pstart = (uint *) CFG_MEMTEST_START;
242 uint *pend = (uint *) CFG_MEMTEST_END;
245 printf("SDRAM test phase 1:\n");
246 for (p = pstart; p < pend; p++)
249 for (p = pstart; p < pend; p++) {
250 if (*p != 0xaaaaaaaa) {
251 printf ("SDRAM test fails at: %08x\n", (uint) p);
256 printf("SDRAM test phase 2:\n");
257 for (p = pstart; p < pend; p++)
260 for (p = pstart; p < pend; p++) {
261 if (*p != 0x55555555) {
262 printf ("SDRAM test fails at: %08x\n", (uint) p);
267 printf("SDRAM test passed.\n");
273 #if !defined(CONFIG_SPD_EEPROM)
274 /*************************************************************************
275 * fixed sdram init -- doesn't use serial presence detect.
276 ************************************************************************/
277 long int fixed_sdram (void)
280 volatile immap_t *immap = (immap_t *)CFG_IMMR;
281 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
283 ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
284 ddr->cs0_config = CFG_DDR_CS0_CONFIG;
285 ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
286 ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
287 ddr->sdram_mode = CFG_DDR_MODE;
288 ddr->sdram_interval = CFG_DDR_INTERVAL;
289 #if defined (CONFIG_DDR_ECC)
290 ddr->err_disable = 0x0000000D;
291 ddr->err_sbe = 0x00ff0000;
293 asm("sync;isync;msync");
295 #if defined (CONFIG_DDR_ECC)
296 /* Enable ECC checking */
297 ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
299 ddr->sdram_cfg = CFG_DDR_CONTROL;
301 asm("sync; isync; msync");
304 return CFG_SDRAM_SIZE * 1024 * 1024;
306 #endif /* !defined(CONFIG_SPD_EEPROM) */
309 #if defined(CONFIG_PCI)
311 * Initialize PCI Devices, report devices found.
314 #ifndef CONFIG_PCI_PNP
315 static struct pci_config_table pci_mpc85xxads_config_table[] = {
316 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
317 PCI_IDSEL_NUMBER, PCI_ANY_ID,
318 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
320 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
327 static struct pci_controller hose = {
328 #ifndef CONFIG_PCI_PNP
329 config_table: pci_mpc85xxads_config_table,
333 #endif /* CONFIG_PCI */
340 extern void pci_mpc85xx_init(struct pci_controller *hose);
342 pci_mpc85xx_init(&hose);
343 #endif /* CONFIG_PCI */