2 * (C) Copyright 2002,2003, Motorola Inc.
3 * Xianghua Xiao, (X.Xiao@motorola.com)
5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
30 #include <asm/immap_85xx.h>
31 #include <asm/fsl_ddr_sdram.h>
32 #include <spd_sdram.h>
34 long int fixed_sdram (void);
36 int board_pre_init (void)
38 #if defined(CONFIG_PCI)
39 volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
41 pci->peer &= 0xffffffdf; /* disable master abort */
50 get_sys_info (&sysinfo);
52 printf ("Board: Freescale MPC8540EVAL Board\n");
53 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor[0] / 1000000);
54 printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
55 printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
56 if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
57 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
58 printf ("\tLBC: %lu MHz\n",
59 sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f));
61 printf("\tLBC: unknown\n");
63 printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
67 phys_size_t initdram (int board_type)
71 #if !defined(CONFIG_RAM_AS_FLASH)
72 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
76 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
77 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
80 #if defined(CONFIG_DDR_DLL)
83 /* Work around to stabilize DDR DLL */
84 temp_ddrdll = gur->ddrdllcr;
85 gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
86 asm("sync;isync;msync");
89 #if defined(CONFIG_SPD_EEPROM)
90 dram_size = fsl_ddr_sdram();
91 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
92 dram_size *= 0x100000;
94 dram_size = fixed_sdram ();
97 #if defined(CONFIG_SYS_RAMBOOT)
101 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
102 get_sys_info(&sysinfo);
103 /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
104 if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
105 lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
107 lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
109 temp_lbcdll = gur->lbcdllcr;
110 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
111 asm("sync;isync;msync");
113 lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
114 lbc->br2 = CONFIG_SYS_BR2_PRELIM;
115 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
116 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
118 * (ulong *)0 = 0x000000ff;
119 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
121 * (ulong *)0 = 0x000000ff;
122 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
124 * (ulong *)0 = 0x000000ff;
125 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
127 * (ulong *)0 = 0x000000ff;
128 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
130 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
132 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
136 #if defined(CONFIG_DDR_ECC)
138 /* Initialize all of memory for ECC, then
142 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
144 for (*p = 0; p < (uint *)(8 * 1024); p++) {
145 if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
146 *p = (unsigned int)0xdeadbeef;
147 if (((unsigned int)p & 0x1c) == 0x1c) { dcbf(p); }
151 dmacpy(0x2000, 0, 0x2000);
153 dmacpy(0x4000, 0, 0x4000);
155 dmacpy(0x8000, 0, 0x8000);
157 dmacpy(0x10000, 0, 0x10000);
159 dmacpy(0x20000, 0, 0x20000);
161 dmacpy(0x40000, 0, 0x40000);
163 dmacpy(0x80000, 0, 0x80000);
165 dmacpy(0x100000, 0, 0x100000);
167 dmacpy(0x200000, 0, 0x200000);
169 dmacpy(0x400000, 0, 0x400000);
171 for (i = 1; i < dram_size / 0x800000; i++)
172 dmacpy(0x800000 * i, 0, 0x800000);
174 /* Enable errors for ECC */
175 ddr->err_disable = 0x00000000;
176 asm("sync;isync;msync");
183 #if defined(CONFIG_SYS_DRAM_TEST)
186 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
187 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
190 printf("SDRAM test phase 1:\n");
191 for (p = pstart; p < pend; p++)
194 for (p = pstart; p < pend; p++) {
195 if (*p != 0xaaaaaaaa) {
196 printf ("SDRAM test fails at: %08x\n", (uint) p);
201 printf("SDRAM test phase 2:\n");
202 for (p = pstart; p < pend; p++)
205 for (p = pstart; p < pend; p++) {
206 if (*p != 0x55555555) {
207 printf ("SDRAM test fails at: %08x\n", (uint) p);
212 printf("SDRAM test passed.\n");
217 #if !defined(CONFIG_SPD_EEPROM)
218 /*************************************************************************
219 * fixed sdram init -- doesn't use serial presence detect.
220 ************************************************************************/
221 long int fixed_sdram (void)
223 #ifndef CONFIG_SYS_RAMBOOT
224 volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
226 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
227 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
228 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
229 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
230 ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
231 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
232 #if defined (CONFIG_DDR_ECC)
233 ddr->err_disable = 0x0000000D;
234 ddr->err_sbe = 0x00ff0000;
236 asm("sync;isync;msync");
238 #if defined (CONFIG_DDR_ECC)
239 /* Enable ECC checking */
240 ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
242 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
244 asm("sync; isync; msync");
247 return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
249 #endif /* !defined(CONFIG_SPD_EEPROM) */
251 int board_eth_init(bd_t *bis)
254 * This board either has PCI NICs or uses the CPU's TSECs
255 * pci_eth_init() will return 0 if no NICs found, so in that case
256 * returning -1 will force cpu_eth_init() to be called.
258 int num = pci_eth_init(bis);
259 return (num <= 0 ? -1 : num);