2 * Copyright 2007 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
28 #include <asm/immap_85xx.h>
29 #include <asm/immap_fsl_pci.h>
34 #include <fdt_support.h>
38 const qe_iop_conf_t qe_iop_conf_tab[] = {
40 {4, 10, 1, 0, 2}, /* TxD0 */
41 {4, 9, 1, 0, 2}, /* TxD1 */
42 {4, 8, 1, 0, 2}, /* TxD2 */
43 {4, 7, 1, 0, 2}, /* TxD3 */
44 {4, 23, 1, 0, 2}, /* TxD4 */
45 {4, 22, 1, 0, 2}, /* TxD5 */
46 {4, 21, 1, 0, 2}, /* TxD6 */
47 {4, 20, 1, 0, 2}, /* TxD7 */
48 {4, 15, 2, 0, 2}, /* RxD0 */
49 {4, 14, 2, 0, 2}, /* RxD1 */
50 {4, 13, 2, 0, 2}, /* RxD2 */
51 {4, 12, 2, 0, 2}, /* RxD3 */
52 {4, 29, 2, 0, 2}, /* RxD4 */
53 {4, 28, 2, 0, 2}, /* RxD5 */
54 {4, 27, 2, 0, 2}, /* RxD6 */
55 {4, 26, 2, 0, 2}, /* RxD7 */
56 {4, 11, 1, 0, 2}, /* TX_EN */
57 {4, 24, 1, 0, 2}, /* TX_ER */
58 {4, 16, 2, 0, 2}, /* RX_DV */
59 {4, 30, 2, 0, 2}, /* RX_ER */
60 {4, 17, 2, 0, 2}, /* RX_CLK */
61 {4, 19, 1, 0, 2}, /* GTX_CLK */
62 {1, 31, 2, 0, 3}, /* GTX125 */
65 {5, 10, 1, 0, 2}, /* TxD0 */
66 {5, 9, 1, 0, 2}, /* TxD1 */
67 {5, 8, 1, 0, 2}, /* TxD2 */
68 {5, 7, 1, 0, 2}, /* TxD3 */
69 {5, 23, 1, 0, 2}, /* TxD4 */
70 {5, 22, 1, 0, 2}, /* TxD5 */
71 {5, 21, 1, 0, 2}, /* TxD6 */
72 {5, 20, 1, 0, 2}, /* TxD7 */
73 {5, 15, 2, 0, 2}, /* RxD0 */
74 {5, 14, 2, 0, 2}, /* RxD1 */
75 {5, 13, 2, 0, 2}, /* RxD2 */
76 {5, 12, 2, 0, 2}, /* RxD3 */
77 {5, 29, 2, 0, 2}, /* RxD4 */
78 {5, 28, 2, 0, 2}, /* RxD5 */
79 {5, 27, 2, 0, 3}, /* RxD6 */
80 {5, 26, 2, 0, 2}, /* RxD7 */
81 {5, 11, 1, 0, 2}, /* TX_EN */
82 {5, 24, 1, 0, 2}, /* TX_ER */
83 {5, 16, 2, 0, 2}, /* RX_DV */
84 {5, 30, 2, 0, 2}, /* RX_ER */
85 {5, 17, 2, 0, 2}, /* RX_CLK */
86 {5, 19, 1, 0, 2}, /* GTX_CLK */
87 {1, 31, 2, 0, 3}, /* GTX125 */
88 {4, 6, 3, 0, 2}, /* MDIO */
89 {4, 5, 1, 0, 2}, /* MDC */
90 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
94 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
95 extern void ddr_enable_ecc(unsigned int dram_size);
98 extern long int spd_sdram(void);
100 void local_bus_init(void);
101 void sdram_init(void);
103 int board_early_init_f (void)
106 * Initialize local bus.
110 enable_8568mds_duart();
111 enable_8568mds_flash_write();
112 #if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
113 enable_8568mds_qe_mdio();
116 #ifdef CFG_I2C2_OFFSET
117 /* Enable I2C2_SCL and I2C2_SDA */
118 volatile struct par_io *port_c;
119 port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
120 port_c->cpdir2 |= 0x0f000000;
121 port_c->cppar2 &= ~0x0f000000;
122 port_c->cppar2 |= 0x0a000000;
128 int checkboard (void)
130 printf ("Board: 8568 MDS\n");
136 initdram(int board_type)
140 puts("Initializing\n");
142 #if defined(CONFIG_DDR_DLL)
145 * Work around to stabilize DDR DLL MSYNC_IN.
146 * Errata DDR9 seems to have been fixed.
147 * This is now the workaround for Errata DDR11:
148 * Override DLL = 1, Course Adj = 1, Tap Select = 0
151 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
153 gur->ddrdllcr = 0x81000000;
154 asm("sync;isync;msync");
158 dram_size = spd_sdram();
160 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
162 * Initialize and enable DDR ECC.
164 ddr_enable_ecc(dram_size);
167 * SDRAM Initialization
176 * Initialize Local Bus
181 volatile immap_t *immap = (immap_t *)CFG_IMMR;
182 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
183 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
189 get_sys_info(&sysinfo);
190 clkdiv = (lbc->lcrr & 0x0f) * 2;
191 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
193 gur->lbiuiplldcr1 = 0x00078080;
195 gur->lbiuiplldcr0 = 0x7c0f1bf0;
196 } else if (clkdiv == 8) {
197 gur->lbiuiplldcr0 = 0x6c0f1bf0;
198 } else if (clkdiv == 4) {
199 gur->lbiuiplldcr0 = 0x5c0f1bf0;
202 lbc->lcrr |= 0x00030000;
204 asm("sync;isync;msync");
208 * Initialize SDRAM memory on the Local Bus.
213 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
216 volatile immap_t *immap = (immap_t *)CFG_IMMR;
217 volatile ccsr_lbc_t *lbc = &immap->im_lbc;
218 uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
223 print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
226 * Setup SDRAM Base and Option Registers
228 lbc->or2 = CFG_OR2_PRELIM;
231 lbc->br2 = CFG_BR2_PRELIM;
234 lbc->lbcr = CFG_LBC_LBCR;
238 lbc->lsrt = CFG_LBC_LSRT;
239 lbc->mrtpr = CFG_LBC_MRTPR;
243 * MPC8568 uses "new" 15-16 style addressing.
245 lsdmr_common = CFG_LBC_LSDMR_COMMON;
246 lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
249 * Issue PRECHARGE ALL command.
251 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
254 ppcDcbf((unsigned long) sdram_addr);
258 * Issue 8 AUTO REFRESH commands.
260 for (idx = 0; idx < 8; idx++) {
261 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
264 ppcDcbf((unsigned long) sdram_addr);
269 * Issue 8 MODE-set command.
271 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
274 ppcDcbf((unsigned long) sdram_addr);
278 * Issue NORMAL OP command.
280 lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
283 ppcDcbf((unsigned long) sdram_addr);
284 udelay(200); /* Overkill. Must wait > 200 bus cycles */
286 #endif /* enable SDRAM init */
289 #if defined(CFG_DRAM_TEST)
293 uint *pstart = (uint *) CFG_MEMTEST_START;
294 uint *pend = (uint *) CFG_MEMTEST_END;
297 printf("Testing DRAM from 0x%08x to 0x%08x\n",
301 printf("DRAM test phase 1:\n");
302 for (p = pstart; p < pend; p++)
305 for (p = pstart; p < pend; p++) {
306 if (*p != 0xaaaaaaaa) {
307 printf ("DRAM test fails at: %08x\n", (uint) p);
312 printf("DRAM test phase 2:\n");
313 for (p = pstart; p < pend; p++)
316 for (p = pstart; p < pend; p++) {
317 if (*p != 0x55555555) {
318 printf ("DRAM test fails at: %08x\n", (uint) p);
323 printf("DRAM test passed.\n");
328 #if defined(CONFIG_PCI)
329 #ifndef CONFIG_PCI_PNP
330 static struct pci_config_table pci_mpc8568mds_config_table[] = {
332 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
333 pci_cfgfunc_config_device,
336 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
342 static struct pci_controller pci1_hose = {
343 #ifndef CONFIG_PCI_PNP
344 config_table: pci_mpc8568mds_config_table,
347 #endif /* CONFIG_PCI */
350 static struct pci_controller pcie1_hose;
351 #endif /* CONFIG_PCIE1 */
353 int first_free_busno = 0;
356 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
361 u8 val8, orig_i2c_bus;
363 * Assign PIB PMC2/3 to PCI bus
366 /*switch temporarily to I2C bus #2 */
367 orig_i2c_bus = i2c_get_bus_num();
371 i2c_write(0x23, 0x6, 1, &val8, 1);
372 i2c_write(0x23, 0x7, 1, &val8, 1);
374 i2c_write(0x23, 0x2, 1, &val8, 1);
375 i2c_write(0x23, 0x3, 1, &val8, 1);
378 i2c_write(0x26, 0x6, 1, &val8, 1);
380 i2c_write(0x26, 0x7, 1, &val8, 1);
382 i2c_write(0x26, 0x2, 1, &val8, 1);
384 i2c_write(0x26, 0x3, 1, &val8, 1);
387 i2c_write(0x27, 0x6, 1, &val8, 1);
388 i2c_write(0x27, 0x7, 1, &val8, 1);
390 i2c_write(0x27, 0x2, 1, &val8, 1);
392 i2c_write(0x27, 0x3, 1, &val8, 1);
401 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
402 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
403 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
409 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
410 extern void fsl_pci_init(struct pci_controller *hose);
411 struct pci_controller *hose = &pci1_hose;
413 uint pci_32 = 1; /* PORDEVSR[15] */
414 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
415 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
417 uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
419 uint pci_speed = 66666000;
421 if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
422 printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
424 (pci_speed == 33333000) ? "33" :
425 (pci_speed == 66666000) ? "66" : "unknown",
426 pci_clk_sel ? "sync" : "async",
427 pci_agent ? "agent" : "host",
428 pci_arb ? "arbiter" : "external-arbiter"
432 pci_set_region(hose->regions + 0,
436 PCI_REGION_MEM | PCI_REGION_MEMORY);
438 /* outbound memory */
439 pci_set_region(hose->regions + 1,
446 pci_set_region(hose->regions + 2,
452 hose->region_count = 3;
454 hose->first_busno = first_free_busno;
455 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
458 first_free_busno = hose->last_busno+1;
459 printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
461 printf (" PCI: disabled\n");
465 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
470 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
471 extern void fsl_pci_init(struct pci_controller *hose);
472 struct pci_controller *hose = &pcie1_hose;
473 int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
475 int pcie_configured = io_sel >= 1;
477 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
478 printf ("\n PCIE connected to slot as %s (base address %x)",
479 pcie_ep ? "End Point" : "Root Complex",
482 if (pci->pme_msg_det) {
483 pci->pme_msg_det = 0xffffffff;
484 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
489 pci_set_region(hose->regions + 0,
493 PCI_REGION_MEM | PCI_REGION_MEMORY);
495 /* outbound memory */
496 pci_set_region(hose->regions + 1,
503 pci_set_region(hose->regions + 2,
509 hose->region_count = 3;
511 hose->first_busno=first_free_busno;
512 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
515 printf ("PCIE on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
517 first_free_busno=hose->last_busno+1;
520 printf (" PCIE: disabled\n");
524 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
527 #endif /* CONFIG_PCI */
529 #if defined(CONFIG_OF_BOARD_SETUP)
531 ft_board_setup(void *blob, bd_t *bd)
536 ft_cpu_setup(blob, bd);
538 node = fdt_path_offset(blob, "/aliases");
542 path = fdt_getprop(blob, node, "pci0", NULL);
544 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
545 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
549 path = fdt_getprop(blob, node, "pci1", NULL);
551 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
552 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);