2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
5 * Adapted for PIP405 03.07.01
6 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
18 DECLARE_GLOBAL_DATA_PTR;
20 #include "piix4_pci.h"
21 #include "pci_parts.h"
23 void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
24 struct pci_config_table *entry)
26 struct pci_pip405_config_entry *table;
29 table = (struct pci_pip405_config_entry*) entry->priv[0];
31 for (i=0; table[i].width; i++)
34 printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
35 table[i].index, table[i].val, table[i].width);
38 switch(table[i].width)
40 case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break;
41 case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break;
42 case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break;
48 static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
50 unsigned char int_line = 0xff;
53 * Write pci interrupt line register
55 if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */
57 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
58 if ((pin == 0) || (pin > 4))
61 int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
62 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
64 printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
65 PCI_DEV(dev),dev,int_line,int_line);
69 extern void pci_405gp_init(struct pci_controller *hose);
72 static struct pci_controller hose = {
73 config_table: pci_pip405_config_table,
74 fixup_irq: pci_pip405_fixup_irq,
78 void pci_init_board(void)
80 /*we want the ptrs to RAM not flash (ie don't use init list)*/
81 hose.fixup_irq = pci_pip405_fixup_irq;
82 hose.config_table = pci_pip405_config_table;
84 printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose);
86 pci_405gp_init(&hose);
89 #endif /* CONFIG_PCI */
90 #endif /* CONFIG_405GP */