1 /*------------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-------------------------------------------------------------------------------*/
22 /*-----------------------------------------------------------------------------
23 * Function: ext_bus_cntlr_init
24 * Description: Initializes the External Bus Controller for the external
25 * peripherals. IMPORTANT: For pass1 this code must run from
26 * cache since you can not reliably change a peripheral banks
27 * timing register (pbxap) while running code from that bank.
28 * For ex., since we are running from ROM on bank 0, we can NOT
29 * execute the code that modifies bank 0 timings from ROM, so
30 * we run it from cache.
31 * Bank 0 - Flash or Multi Purpose Socket
32 * Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
33 * Bank 2 - UART 1 (set in C-Code)
34 * Bank 3 - UART 2 (set in C-Code)
38 * Bank 7 - PLD Register
39 *-----------------------------------------------------------------------------*/
42 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
44 #include <configs/MIP405.h>
45 #include <ppc_asm.tmpl>
48 #include <asm/cache.h>
53 .globl ext_bus_cntlr_init
55 mflr r4 /* save link register */
56 mfdcr r3,strap /* get strapping reg */
57 andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
58 bnelr /* jump back if PCI boot */
62 mflr r3 /* get address of ..getAddr */
63 mtlr r4 /* restore link register */
64 addi r4,0,14 /* set ctr to 14; used to prefetch */
65 mtctr r4 /* 14 cache lines to fit this function */
66 /* in cache (gives us 8x14=112 instrctns) */
68 icbt r0,r3 /* prefetch cache line for addr in r3 */
69 addi r3,r3,32 /* move to next cache line */
70 bdnz ..ebcloop /* continue for 14 cache lines */
72 /*-------------------------------------------------------------------
73 * Delay to ensure all accesses to ROM are complete before changing
75 *------------------------------------------------------------------- */
80 bdnz ..spinlp /* spin loop */
82 /*-----------------------------------------------------------------------
84 *----------------------------------------------------------------------- */
89 andi. r0, r4, 0x2000 /* mask out irrelevant bits */
90 beq 0f /* jump if 8 bit bus width */
92 /* setup 16 bit things
93 *-----------------------------------------------------------------------
94 * Memory Bank 0 (16 Bit Flash) initialization
95 *---------------------------------------------------------------------- */
99 addis r4,0,(FLASH_AP_B)@h
100 ori r4,r4,(FLASH_AP_B)@l
105 /* BS=0x010(4MB),BU=0x3(R/W), */
106 addis r4,0,(FLASH_CR_B)@h
107 ori r4,r4,(FLASH_CR_B)@l
113 /* 8Bit boot mode: */
114 /*-----------------------------------------------------------------------
115 * Memory Bank 0 Multi Purpose Socket initialization
116 *----------------------------------------------------------------------- */
117 /* 0x7F8FFE80 slowest boot */
120 addis r4,0,(MPS_AP_B)@h
121 ori r4,r4,(MPS_AP_B)@l
126 /* BS=0x010(4MB),BU=0x3(R/W), */
127 addis r4,0,(MPS_CR_B)@h
128 ori r4,r4,(MPS_CR_B)@l
134 /*-----------------------------------------------------------------------
135 * Memory Bank 2-3-4-5-6 (not used) initialization
136 *-----------------------------------------------------------------------*/
178 nop /* pass2 DCR errata #8 */
181 #if defined(CONFIG_BOOT_PCI)
182 .section .bootpg,"ax"
184 /*******************************************
188 /* first handle errata #68 / PCI_18 */
189 iccci r0, r0 /* invalidate I-cache */
191 mticcr r31 /* ICCR = 0 (all uncachable) */
194 mfccr0 r28 /* set CCR0[24] = 1 */
198 /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
200 addi r28, r28, 0x0004
201 stw r31, 0x0C(r28) /* clear PMM0PCIHA */
202 lis r29, 0xFFF8 /* open 512 kByte */
203 addi r29, r29, 0x0001/* and enable this region */
204 stwbrx r29, r0, r28 /* write PMM0MA */
206 lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
207 addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
209 lis r31, 0x8000 /* set en bit bus 0 */
210 ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
211 stwbrx r31, r0, r28 /* write it */
213 lwbrx r31, r0, r29 /* load XBCS register */
214 oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
215 stwbrx r31, r0, r29 /* write back XBCS register */
219 b _start /* normal start */