3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
30 * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
31 * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
32 * parameters from the datasheet are:
33 * Tclk = 7.5ns (CL = 2)
39 * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
40 * period is 10ns and the parameters needed for the Timing Register are:
41 * CASL = CL = 2 clock cycles
42 * PTA = Trp = 15ns / 10ns = 2 clock cycles
43 * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
44 * LDF = 2 clock cycles (but can be extended to meet board-level timing)
45 * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
46 * RCD = Trcd = 15ns / 10ns= 2 clock cycles
48 * The actual bit settings in the register would be:
57 * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
58 * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
59 * defined as Trc rather than Trfc.
60 * When using DIMM modules, most but not all of the required timing parameters can be read
61 * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
62 * are not available from the EEPROM
67 #include <asm/processor.h>
68 #include <asm/ppc4xx.h>
69 #include <asm/ppc4xx-i2c.h>
71 #include "../common/common_util.h"
72 #include <stdio_dev.h>
76 DECLARE_GLOBAL_DATA_PTR;
79 #define ENABLE_ECC /* for ecc boards */
83 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
84 #ifndef __ldiv_t_defined
86 long int quot; /* Quotient */
87 long int rem; /* Remainder */
89 extern ldiv_t ldiv (long int __numer, long int __denom);
90 # define __ldiv_t_defined 1
94 #define PLD_PART_REG PER_PLD_ADDR + 0
95 #define PLD_VERS_REG PER_PLD_ADDR + 1
96 #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
97 #define PLD_IRQ_REG PER_PLD_ADDR + 3
98 #define PLD_COM_MODE_REG PER_PLD_ADDR + 4
99 #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
101 #define MEGA_BYTE (1024*1024)
104 unsigned char boardtype; /* Board revision and Population Options */
105 unsigned char cal; /* cas Latency (will be programmend as cal-1) */
106 unsigned char trp; /* datain27 in clocks */
107 unsigned char trcd; /* datain29 in clocks */
108 unsigned char tras; /* datain30 in clocks */
109 unsigned char tctp; /* tras - trcd in clocks */
110 unsigned char am; /* Address Mod (will be programmed as am-1) */
111 unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
112 unsigned char ecc; /* if true, ecc is enabled */
114 #if defined(CONFIG_MIP405T)
115 const sdram_t sdram_table[] = {
116 { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
117 3, /* Case Latenty = 3 */
118 3, /* trp 20ns / 7.5 ns datain[27] */
119 3, /* trcd 20ns /7.5 ns (datain[29]) */
120 6, /* tras 44ns /7.5 ns (datain[30]) */
121 4, /* tcpt 44 - 20ns = 24ns */
122 2, /* Address Mode = 2 (12x9x4) */
123 3, /* size value (32MByte) */
124 0}, /* ECC disabled */
125 { 0xff, /* terminator */
135 const sdram_t sdram_table[] = {
136 { 0x0f, /* Rev A, 128MByte -1 Board */
137 3, /* Case Latenty = 3 */
138 3, /* trp 20ns / 7.5 ns datain[27] */
139 3, /* trcd 20ns /7.5 ns (datain[29]) */
140 6, /* tras 44ns /7.5 ns (datain[30]) */
141 4, /* tcpt 44 - 20ns = 24ns */
142 3, /* Address Mode = 3 */
144 1}, /* ECC enabled */
145 { 0x07, /* Rev A, 64MByte -2 Board */
146 3, /* Case Latenty = 3 */
147 3, /* trp 20ns / 7.5 ns datain[27] */
148 3, /* trcd 20ns /7.5 ns (datain[29]) */
149 6, /* tras 44ns /7.5 ns (datain[30]) */
150 4, /* tcpt 44 - 20ns = 24ns */
151 2, /* Address Mode = 2 */
153 1}, /* ECC enabled */
154 { 0x03, /* Rev A, 128MByte -4 Board */
155 3, /* Case Latenty = 3 */
156 3, /* trp 20ns / 7.5 ns datain[27] */
157 3, /* trcd 20ns /7.5 ns (datain[29]) */
158 6, /* tras 44ns /7.5 ns (datain[30]) */
159 4, /* tcpt 44 - 20ns = 24ns */
160 3, /* Address Mode = 3 */
162 1}, /* ECC enabled */
163 { 0x1f, /* Rev B, 128MByte -3 Board */
164 3, /* Case Latenty = 3 */
165 3, /* trp 20ns / 7.5 ns datain[27] */
166 3, /* trcd 20ns /7.5 ns (datain[29]) */
167 6, /* tras 44ns /7.5 ns (datain[30]) */
168 4, /* tcpt 44 - 20ns = 24ns */
169 3, /* Address Mode = 3 */
171 1}, /* ECC enabled */
172 { 0x2f, /* Rev C, 128MByte -3 Board */
173 3, /* Case Latenty = 3 */
174 3, /* trp 20ns / 7.5 ns datain[27] */
175 3, /* trcd 20ns /7.5 ns (datain[29]) */
176 6, /* tras 44ns /7.5 ns (datain[30]) */
177 4, /* tcpt 44 - 20ns = 24ns */
178 3, /* Address Mode = 3 */
180 1}, /* ECC enabled */
181 { 0xff, /* terminator */
190 #endif /*CONFIG_MIP405T */
191 void SDRAM_err (const char *s)
194 (void) get_clocks ();
200 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
205 unsigned char get_board_revcfg (void)
207 out8 (PER_BOARD_ADDR, 0);
208 return (in8 (PER_BOARD_ADDR));
214 void write_hex (unsigned char i)
221 serial_putc (cc + 55);
223 serial_putc (cc + 48);
226 serial_putc (cc + 55);
228 serial_putc (cc + 48);
231 void write_4hex (unsigned long val)
233 write_hex ((unsigned char) (val >> 24));
234 write_hex ((unsigned char) (val >> 16));
235 write_hex ((unsigned char) (val >> 8));
236 write_hex ((unsigned char) val);
242 int init_sdram (void)
244 unsigned long tmp, baseaddr;
246 unsigned char trp_clocks,
250 unsigned char cal_val;
252 unsigned long sdram_tim, sdram_bank;
254 /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
255 (void) get_clocks ();
259 mtdcr (EBC0_CFGADDR, PB7AP);
260 mtdcr (EBC0_CFGDATA, PLD_AP);
261 mtdcr (EBC0_CFGADDR, PB7CR);
262 mtdcr (EBC0_CFGDATA, PLD_CR);
263 /* THIS IS OBSOLETE */
264 /* set up the board rev reg*/
265 mtdcr (EBC0_CFGADDR, PB5AP);
266 mtdcr (EBC0_CFGDATA, BOARD_AP);
267 mtdcr (EBC0_CFGADDR, PB5CR);
268 mtdcr (EBC0_CFGDATA, BOARD_CR);
270 /* get all informations from PLD */
271 serial_puts ("\nPLD Part 0x");
272 bc = in8 (PLD_PART_REG);
274 serial_puts ("\nPLD Vers 0x");
275 bc = in8 (PLD_VERS_REG);
277 serial_puts ("\nBoard Rev 0x");
278 bc = in8 (PLD_BOARD_CFG_REG);
283 bc = in8 (PLD_PART_REG);
284 #if defined(CONFIG_MIP405T)
286 SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
288 if((bc & 0x80)==0x80)
289 SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
291 /* set-up the chipselect machine */
292 mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */
293 tmp = mfdcr (EBC0_CFGDATA);
294 if ((tmp & 0x00002000) == 0) {
295 /* MPS Boot, set up the flash */
296 mtdcr (EBC0_CFGADDR, PB1AP);
297 mtdcr (EBC0_CFGDATA, FLASH_AP);
298 mtdcr (EBC0_CFGADDR, PB1CR);
299 mtdcr (EBC0_CFGDATA, FLASH_CR);
301 /* Flash boot, set up the MPS */
302 mtdcr (EBC0_CFGADDR, PB1AP);
303 mtdcr (EBC0_CFGDATA, MPS_AP);
304 mtdcr (EBC0_CFGADDR, PB1CR);
305 mtdcr (EBC0_CFGDATA, MPS_CR);
307 /* set up UART0 (CS2) and UART1 (CS3) */
308 mtdcr (EBC0_CFGADDR, PB2AP);
309 mtdcr (EBC0_CFGDATA, UART0_AP);
310 mtdcr (EBC0_CFGADDR, PB2CR);
311 mtdcr (EBC0_CFGDATA, UART0_CR);
312 mtdcr (EBC0_CFGADDR, PB3AP);
313 mtdcr (EBC0_CFGDATA, UART1_AP);
314 mtdcr (EBC0_CFGADDR, PB3CR);
315 mtdcr (EBC0_CFGDATA, UART1_CR);
316 bc = in8 (PLD_BOARD_CFG_REG);
318 serial_puts ("\nstart SDRAM Setup\n");
319 serial_puts ("\nBoard Rev: ");
324 baseaddr = CONFIG_SYS_SDRAM_BASE;
325 while (sdram_table[i].sz != 0xff) {
326 if (sdram_table[i].boardtype == bc)
330 if (sdram_table[i].boardtype != bc)
331 SDRAM_err ("No SDRAM table found for this board!!!\n");
333 serial_puts (" found table ");
337 /* since the ECC initialisation needs some time,
338 * we show that we're alive
340 if (sdram_table[i].ecc)
341 serial_puts ("\nInitializing SDRAM, Please stand by");
342 cal_val = sdram_table[i].cal - 1; /* Cas Latency */
343 trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
344 trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
345 tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
346 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
347 /* trc_clocks is sum of trp_clocks + tras_clocks */
348 trc_clocks = trp_clocks + tras_clocks;
349 /* get SDRAM timing register */
350 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
351 sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
352 /* insert CASL value */
353 sdram_tim |= ((unsigned long) (cal_val)) << 23;
354 /* insert PTA value */
355 sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
356 /* insert CTP value */
358 ((unsigned long) (trc_clocks - trp_clocks -
360 /* insert LDF (always 01) */
361 sdram_tim |= ((unsigned long) 0x01) << 14;
362 /* insert RFTA value */
363 sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
364 /* insert RCD value */
365 sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
367 tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
368 /* insert SZ value; */
369 tmp |= ((unsigned long) sdram_table[i].sz << 17);
370 /* get SDRAM bank 0 register */
371 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
372 sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
373 sdram_bank |= (baseaddr | tmp | 0x01);
376 serial_puts ("sdtr: ");
377 write_4hex (sdram_tim);
381 /* write SDRAM timing register */
382 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
383 mtdcr (SDRAM0_CFGDATA, sdram_tim);
386 serial_puts ("mb0cf: ");
387 write_4hex (sdram_bank);
391 /* write SDRAM bank 0 register */
392 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
393 mtdcr (SDRAM0_CFGDATA, sdram_bank);
395 if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
396 /* get SDRAM refresh interval register */
397 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
398 tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
401 /* get SDRAM refresh interval register */
402 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
403 tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
406 /* write SDRAM refresh interval register */
407 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
408 mtdcr (SDRAM0_CFGDATA, tmp);
409 /* enable ECC if used */
410 #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
411 if (sdram_table[i].ecc) {
412 /* disable checking for all banks */
415 serial_puts ("disable ECC.. ");
417 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
418 tmp = mfdcr (SDRAM0_CFGDATA);
419 tmp &= 0xff0fffff; /* disable all banks */
420 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
421 /* set up SDRAM Controller with ECC enabled */
423 serial_puts ("setup SDRAM Controller.. ");
425 mtdcr (SDRAM0_CFGDATA, tmp);
426 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
427 tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
428 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
429 mtdcr (SDRAM0_CFGDATA, tmp);
432 serial_puts ("fill the memory..\n");
435 /* now, fill all the memory */
436 tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
437 p = (unsigned long) 0;
438 while ((unsigned long) p < tmp) {
440 if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
446 serial_puts ("enable ECC\n");
449 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
450 tmp = mfdcr (SDRAM0_CFGDATA);
451 tmp |= 0x00800000; /* enable bank 0 */
452 mtdcr (SDRAM0_CFGDATA, tmp);
457 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
458 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
459 tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
460 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
461 mtdcr (SDRAM0_CFGDATA, tmp);
468 int board_early_init_f (void)
472 /*-------------------------------------------------------------------------+
473 | Interrupt controller setup for the PIP405 board.
474 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
475 | IRQ 16 405GP internally generated; active low; level sensitive
477 | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
478 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
479 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
480 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
481 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
482 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
483 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
484 | Note for MIP405 board:
485 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
486 | the Interrupt Controller in the South Bridge has caused the
487 | interrupt. The IC must be read to determine which device
488 | caused the interrupt.
490 +-------------------------------------------------------------------------*/
491 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
492 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
493 mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
494 mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
495 mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
496 mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
497 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
501 int board_early_init_r(void)
506 * since we are relocated, we can finally enable i-cache
507 * and set up the flash CS correctly
511 /* get and display boot mode */
512 mode = get_boot_mode();
514 printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
517 printf("%s Boot\n", (mode & BOOT_MPS) ?
524 * Get some PLD Registers
527 unsigned short get_pld_parvers (void)
529 unsigned short result;
532 rc = in8 (PLD_PART_REG);
533 result = (unsigned short) rc << 8;
534 rc = in8 (PLD_VERS_REG);
540 void user_led0 (unsigned char on)
543 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
545 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
549 void ide_set_reset (int idereset)
551 /* if reset = 1 IDE reset will be asserted */
553 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
556 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
561 /* ------------------------------------------------------------------------- */
563 void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
565 #if !defined(CONFIG_MIP405T)
566 unsigned char bc,rc,tmp;
569 bc = in8 (PLD_BOARD_CFG_REG);
573 for (i = 0; i < 4; i++) {
579 if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
580 || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
581 && (rc==0x1)) /* Population Option 1 is a -3 */
583 *pcbrev=(bc >> 4) & 0xf;
587 bc = in8 (PLD_BOARD_CFG_REG);
588 *pcbrev=(bc >> 4) & 0xf;
594 * Check Board Identity:
596 /* serial String: "MIP405_1000" OR "MIP405T_1000" */
597 #if !defined(CONFIG_MIP405T)
598 #define BOARD_NAME "MIP405"
600 #define BOARD_NAME "MIP405T"
603 int checkboard (void)
606 unsigned char bc, var;
608 backup_t *b = (backup_t *) s;
611 get_pcbrev_var(&bc,&var);
612 i = getenv_f("serial#", (char *)s, 32);
613 if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
614 get_backup_values (b);
615 if (strncmp (b->signature, "MPL\0", 4) != 0) {
616 puts ("### No HW ID - assuming " BOARD_NAME);
617 printf ("-%d Rev %c", var, 'A' + bc);
619 b->serial_name[sizeof(BOARD_NAME)-1] = 0;
620 printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
621 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
624 s[sizeof(BOARD_NAME)-1] = 0;
625 printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
626 &s[sizeof(BOARD_NAME)]);
628 bc = in8 (PLD_EXT_CONF_REG);
629 printf (" Boot Config: 0x%x\n", bc);
634 /* ------------------------------------------------------------------------- */
635 /* ------------------------------------------------------------------------- */
637 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
638 the necessary info for SDRAM controller configuration
640 /* ------------------------------------------------------------------------- */
641 /* ------------------------------------------------------------------------- */
642 static int test_dram (unsigned long ramsize);
644 phys_size_t initdram (int board_type)
647 unsigned long bank_reg[4], tmp, bank_size;
649 unsigned long TotalSize;
651 /* since the DRAM controller is allready set up, calculate the size with the
653 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
654 bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
655 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
656 bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
657 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
658 bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
659 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
660 bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
662 for (i = 0; i < 4; i++) {
663 if ((bank_reg[i] & 0x1) == 0x1) {
664 tmp = (bank_reg[i] >> 17) & 0x7;
665 bank_size = 4 << tmp;
666 TotalSize += bank_size;
669 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
670 tmp = mfdcr (SDRAM0_CFGDATA);
676 test_dram (TotalSize * MEGA_BYTE);
677 return (TotalSize * MEGA_BYTE);
680 /* ------------------------------------------------------------------------- */
683 static int test_dram (unsigned long ramsize)
686 mem_test (0L, ramsize, 1);
688 /* not yet implemented */
692 /* used to check if the time in RTC is valid */
693 static unsigned long start;
694 static struct rtc_time tm;
696 int misc_init_r (void)
698 /* adjust flash start and size as well as the offset */
699 gd->bd->bi_flashstart=0-flash_info[0].size;
700 gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
701 gd->bd->bi_flashoffset=0;
703 /* check, if RTC is running */
706 /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
707 if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
708 mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
714 void print_mip405_rev (void)
716 unsigned char part, vers, pcbrev, var;
718 get_pcbrev_var(&pcbrev,&var);
719 part = in8 (PLD_PART_REG);
720 vers = in8 (PLD_VERS_REG);
721 printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
722 var, pcbrev + 'A', part & 0x7F, vers);
726 extern int mk_date (char *, struct rtc_time *);
728 int last_stage_init (void)
731 struct rtc_time newtm;
734 /* write correct LED configuration */
735 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
736 printf ("Error writing to the PHY\n");
738 /* since LED/CFG2 is not connected on the -2,
739 * write to correct capability information */
740 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
741 printf ("Error writing to the PHY\n");
744 stdio_print_current_devices ();
746 /* check if RTC time is valid */
747 stop=get_timer(start);
748 while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */
750 stop=get_timer(start);
753 if(tm.tm_sec==newtm.tm_sec) {
754 s=getenv("defaultdate");
756 mk_date ("010112001970", &newtm);
758 if(mk_date (s, &newtm)!=0) {
759 printf("RTC: Bad date format in defaultdate\n");
768 /***************************************************************************
769 * some helping routines
772 int overwrite_console (void)
774 return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */
778 /************************************************************************
780 ************************************************************************/
781 void print_mip405_info (void)
783 unsigned char part, vers, cfg, irq_reg, com_mode, ext;
785 part = in8 (PLD_PART_REG);
786 vers = in8 (PLD_VERS_REG);
787 cfg = in8 (PLD_BOARD_CFG_REG);
788 irq_reg = in8 (PLD_IRQ_REG);
789 com_mode = in8 (PLD_COM_MODE_REG);
790 ext = in8 (PLD_EXT_CONF_REG);
792 printf ("PLD Part %d version %d\n", part & 0x7F, vers);
793 printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
794 printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
795 (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
796 printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
797 printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
798 #if !defined(CONFIG_MIP405T)
799 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
800 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
801 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
802 (ext >> 6) & 0x1, (ext >> 7) & 0x1);
803 printf ("SER1 uses handshakes %s\n",
804 (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
806 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
807 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
808 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
809 (ext >> 6) & 0x1,(ext >> 7) & 0x1);
811 printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
813 printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
814 #if !defined(CONFIG_MIP405T)
815 printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
816 printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
818 printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
819 printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
820 printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");