3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
30 * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
31 * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
32 * parameters from the datasheet are:
33 * Tclk = 7.5ns (CL = 2)
39 * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
40 * period is 10ns and the parameters needed for the Timing Register are:
41 * CASL = CL = 2 clock cycles
42 * PTA = Trp = 15ns / 10ns = 2 clock cycles
43 * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
44 * LDF = 2 clock cycles (but can be extended to meet board-level timing)
45 * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
46 * RCD = Trcd = 15ns / 10ns= 2 clock cycles
48 * The actual bit settings in the register would be:
57 * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
58 * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
59 * defined as Trc rather than Trfc.
60 * When using DIMM modules, most but not all of the required timing parameters can be read
61 * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
62 * are not available from the EEPROM
67 #include <asm/processor.h>
68 #include <asm/ppc4xx.h>
69 #include <asm/ppc4xx-i2c.h>
71 #include "../common/common_util.h"
72 #include <stdio_dev.h>
76 DECLARE_GLOBAL_DATA_PTR;
79 #define ENABLE_ECC /* for ecc boards */
81 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
82 #ifndef __ldiv_t_defined
84 long int quot; /* Quotient */
85 long int rem; /* Remainder */
87 extern ldiv_t ldiv (long int __numer, long int __denom);
88 # define __ldiv_t_defined 1
92 #define PLD_PART_REG PER_PLD_ADDR + 0
93 #define PLD_VERS_REG PER_PLD_ADDR + 1
94 #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
95 #define PLD_IRQ_REG PER_PLD_ADDR + 3
96 #define PLD_COM_MODE_REG PER_PLD_ADDR + 4
97 #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
99 #define MEGA_BYTE (1024*1024)
102 unsigned char boardtype; /* Board revision and Population Options */
103 unsigned char cal; /* cas Latency (will be programmend as cal-1) */
104 unsigned char trp; /* datain27 in clocks */
105 unsigned char trcd; /* datain29 in clocks */
106 unsigned char tras; /* datain30 in clocks */
107 unsigned char tctp; /* tras - trcd in clocks */
108 unsigned char am; /* Address Mod (will be programmed as am-1) */
109 unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
110 unsigned char ecc; /* if true, ecc is enabled */
112 #if defined(CONFIG_MIP405T)
113 const sdram_t sdram_table[] = {
114 { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
115 3, /* Case Latenty = 3 */
116 3, /* trp 20ns / 7.5 ns datain[27] */
117 3, /* trcd 20ns /7.5 ns (datain[29]) */
118 6, /* tras 44ns /7.5 ns (datain[30]) */
119 4, /* tcpt 44 - 20ns = 24ns */
120 2, /* Address Mode = 2 (12x9x4) */
121 3, /* size value (32MByte) */
122 0}, /* ECC disabled */
123 { 0xff, /* terminator */
133 const sdram_t sdram_table[] = {
134 { 0x0f, /* Rev A, 128MByte -1 Board */
135 3, /* Case Latenty = 3 */
136 3, /* trp 20ns / 7.5 ns datain[27] */
137 3, /* trcd 20ns /7.5 ns (datain[29]) */
138 6, /* tras 44ns /7.5 ns (datain[30]) */
139 4, /* tcpt 44 - 20ns = 24ns */
140 3, /* Address Mode = 3 */
142 1}, /* ECC enabled */
143 { 0x07, /* Rev A, 64MByte -2 Board */
144 3, /* Case Latenty = 3 */
145 3, /* trp 20ns / 7.5 ns datain[27] */
146 3, /* trcd 20ns /7.5 ns (datain[29]) */
147 6, /* tras 44ns /7.5 ns (datain[30]) */
148 4, /* tcpt 44 - 20ns = 24ns */
149 2, /* Address Mode = 2 */
151 1}, /* ECC enabled */
152 { 0x03, /* Rev A, 128MByte -4 Board */
153 3, /* Case Latenty = 3 */
154 3, /* trp 20ns / 7.5 ns datain[27] */
155 3, /* trcd 20ns /7.5 ns (datain[29]) */
156 6, /* tras 44ns /7.5 ns (datain[30]) */
157 4, /* tcpt 44 - 20ns = 24ns */
158 3, /* Address Mode = 3 */
160 1}, /* ECC enabled */
161 { 0x1f, /* Rev B, 128MByte -3 Board */
162 3, /* Case Latenty = 3 */
163 3, /* trp 20ns / 7.5 ns datain[27] */
164 3, /* trcd 20ns /7.5 ns (datain[29]) */
165 6, /* tras 44ns /7.5 ns (datain[30]) */
166 4, /* tcpt 44 - 20ns = 24ns */
167 3, /* Address Mode = 3 */
169 1}, /* ECC enabled */
170 { 0x2f, /* Rev C, 128MByte -3 Board */
171 3, /* Case Latenty = 3 */
172 3, /* trp 20ns / 7.5 ns datain[27] */
173 3, /* trcd 20ns /7.5 ns (datain[29]) */
174 6, /* tras 44ns /7.5 ns (datain[30]) */
175 4, /* tcpt 44 - 20ns = 24ns */
176 3, /* Address Mode = 3 */
178 1}, /* ECC enabled */
179 { 0xff, /* terminator */
188 #endif /*CONFIG_MIP405T */
189 void SDRAM_err (const char *s)
192 (void) get_clocks ();
198 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
203 unsigned char get_board_revcfg (void)
205 out8 (PER_BOARD_ADDR, 0);
206 return (in8 (PER_BOARD_ADDR));
212 void write_hex (unsigned char i)
219 serial_putc (cc + 55);
221 serial_putc (cc + 48);
224 serial_putc (cc + 55);
226 serial_putc (cc + 48);
229 void write_4hex (unsigned long val)
231 write_hex ((unsigned char) (val >> 24));
232 write_hex ((unsigned char) (val >> 16));
233 write_hex ((unsigned char) (val >> 8));
234 write_hex ((unsigned char) val);
240 int init_sdram (void)
242 unsigned long tmp, baseaddr;
244 unsigned char trp_clocks,
248 unsigned char cal_val;
250 unsigned long sdram_tim, sdram_bank;
252 /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
253 (void) get_clocks ();
257 mtdcr (EBC0_CFGADDR, PB7AP);
258 mtdcr (EBC0_CFGDATA, PLD_AP);
259 mtdcr (EBC0_CFGADDR, PB7CR);
260 mtdcr (EBC0_CFGDATA, PLD_CR);
261 /* THIS IS OBSOLETE */
262 /* set up the board rev reg*/
263 mtdcr (EBC0_CFGADDR, PB5AP);
264 mtdcr (EBC0_CFGDATA, BOARD_AP);
265 mtdcr (EBC0_CFGADDR, PB5CR);
266 mtdcr (EBC0_CFGDATA, BOARD_CR);
268 /* get all informations from PLD */
269 serial_puts ("\nPLD Part 0x");
270 bc = in8 (PLD_PART_REG);
272 serial_puts ("\nPLD Vers 0x");
273 bc = in8 (PLD_VERS_REG);
275 serial_puts ("\nBoard Rev 0x");
276 bc = in8 (PLD_BOARD_CFG_REG);
281 bc = in8 (PLD_PART_REG);
282 #if defined(CONFIG_MIP405T)
284 SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
286 if((bc & 0x80)==0x80)
287 SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
289 /* set-up the chipselect machine */
290 mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */
291 tmp = mfdcr (EBC0_CFGDATA);
292 if ((tmp & 0x00002000) == 0) {
293 /* MPS Boot, set up the flash */
294 mtdcr (EBC0_CFGADDR, PB1AP);
295 mtdcr (EBC0_CFGDATA, FLASH_AP);
296 mtdcr (EBC0_CFGADDR, PB1CR);
297 mtdcr (EBC0_CFGDATA, FLASH_CR);
299 /* Flash boot, set up the MPS */
300 mtdcr (EBC0_CFGADDR, PB1AP);
301 mtdcr (EBC0_CFGDATA, MPS_AP);
302 mtdcr (EBC0_CFGADDR, PB1CR);
303 mtdcr (EBC0_CFGDATA, MPS_CR);
305 /* set up UART0 (CS2) and UART1 (CS3) */
306 mtdcr (EBC0_CFGADDR, PB2AP);
307 mtdcr (EBC0_CFGDATA, UART0_AP);
308 mtdcr (EBC0_CFGADDR, PB2CR);
309 mtdcr (EBC0_CFGDATA, UART0_CR);
310 mtdcr (EBC0_CFGADDR, PB3AP);
311 mtdcr (EBC0_CFGDATA, UART1_AP);
312 mtdcr (EBC0_CFGADDR, PB3CR);
313 mtdcr (EBC0_CFGDATA, UART1_CR);
314 bc = in8 (PLD_BOARD_CFG_REG);
316 serial_puts ("\nstart SDRAM Setup\n");
317 serial_puts ("\nBoard Rev: ");
322 baseaddr = CONFIG_SYS_SDRAM_BASE;
323 while (sdram_table[i].sz != 0xff) {
324 if (sdram_table[i].boardtype == bc)
328 if (sdram_table[i].boardtype != bc)
329 SDRAM_err ("No SDRAM table found for this board!!!\n");
331 serial_puts (" found table ");
335 /* since the ECC initialisation needs some time,
336 * we show that we're alive
338 if (sdram_table[i].ecc)
339 serial_puts ("\nInitializing SDRAM, Please stand by");
340 cal_val = sdram_table[i].cal - 1; /* Cas Latency */
341 trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
342 trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
343 tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
344 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
345 /* trc_clocks is sum of trp_clocks + tras_clocks */
346 trc_clocks = trp_clocks + tras_clocks;
347 /* get SDRAM timing register */
348 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
349 sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
350 /* insert CASL value */
351 sdram_tim |= ((unsigned long) (cal_val)) << 23;
352 /* insert PTA value */
353 sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
354 /* insert CTP value */
356 ((unsigned long) (trc_clocks - trp_clocks -
358 /* insert LDF (always 01) */
359 sdram_tim |= ((unsigned long) 0x01) << 14;
360 /* insert RFTA value */
361 sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
362 /* insert RCD value */
363 sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
365 tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
366 /* insert SZ value; */
367 tmp |= ((unsigned long) sdram_table[i].sz << 17);
368 /* get SDRAM bank 0 register */
369 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
370 sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
371 sdram_bank |= (baseaddr | tmp | 0x01);
374 serial_puts ("sdtr: ");
375 write_4hex (sdram_tim);
379 /* write SDRAM timing register */
380 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
381 mtdcr (SDRAM0_CFGDATA, sdram_tim);
384 serial_puts ("mb0cf: ");
385 write_4hex (sdram_bank);
389 /* write SDRAM bank 0 register */
390 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
391 mtdcr (SDRAM0_CFGDATA, sdram_bank);
393 if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
394 /* get SDRAM refresh interval register */
395 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
396 tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
399 /* get SDRAM refresh interval register */
400 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
401 tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
404 /* write SDRAM refresh interval register */
405 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
406 mtdcr (SDRAM0_CFGDATA, tmp);
407 /* enable ECC if used */
408 #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
409 if (sdram_table[i].ecc) {
410 /* disable checking for all banks */
413 serial_puts ("disable ECC.. ");
415 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
416 tmp = mfdcr (SDRAM0_CFGDATA);
417 tmp &= 0xff0fffff; /* disable all banks */
418 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
419 /* set up SDRAM Controller with ECC enabled */
421 serial_puts ("setup SDRAM Controller.. ");
423 mtdcr (SDRAM0_CFGDATA, tmp);
424 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
425 tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
426 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
427 mtdcr (SDRAM0_CFGDATA, tmp);
430 serial_puts ("fill the memory..\n");
433 /* now, fill all the memory */
434 tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
435 p = (unsigned long) 0;
436 while ((unsigned long) p < tmp) {
438 if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
444 serial_puts ("enable ECC\n");
447 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
448 tmp = mfdcr (SDRAM0_CFGDATA);
449 tmp |= 0x00800000; /* enable bank 0 */
450 mtdcr (SDRAM0_CFGDATA, tmp);
455 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
456 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
457 tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
458 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
459 mtdcr (SDRAM0_CFGDATA, tmp);
466 int board_early_init_f (void)
470 /*-------------------------------------------------------------------------+
471 | Interrupt controller setup for the PIP405 board.
472 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
473 | IRQ 16 405GP internally generated; active low; level sensitive
475 | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
476 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
477 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
478 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
479 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
480 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
481 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
482 | Note for MIP405 board:
483 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
484 | the Interrupt Controller in the South Bridge has caused the
485 | interrupt. The IC must be read to determine which device
486 | caused the interrupt.
488 +-------------------------------------------------------------------------*/
489 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
490 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
491 mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
492 mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
493 mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
494 mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
495 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
499 int board_early_init_r(void)
504 * since we are relocated, we can finally enable i-cache
505 * and set up the flash CS correctly
509 /* get and display boot mode */
510 mode = get_boot_mode();
512 printf("PCI Boot %s Map\n", (mode & BOOT_MPS) ?
515 printf("%s Boot\n", (mode & BOOT_MPS) ?
522 * Get some PLD Registers
525 unsigned short get_pld_parvers (void)
527 unsigned short result;
530 rc = in8 (PLD_PART_REG);
531 result = (unsigned short) rc << 8;
532 rc = in8 (PLD_VERS_REG);
538 void user_led0 (unsigned char on)
541 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
543 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
547 void ide_set_reset (int idereset)
549 /* if reset = 1 IDE reset will be asserted */
551 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
554 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
559 /* ------------------------------------------------------------------------- */
561 void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
563 #if !defined(CONFIG_MIP405T)
564 unsigned char bc,rc,tmp;
567 bc = in8 (PLD_BOARD_CFG_REG);
571 for (i = 0; i < 4; i++) {
577 if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
578 || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
579 && (rc==0x1)) /* Population Option 1 is a -3 */
581 *pcbrev=(bc >> 4) & 0xf;
585 bc = in8 (PLD_BOARD_CFG_REG);
586 *pcbrev=(bc >> 4) & 0xf;
592 * Check Board Identity:
594 /* serial String: "MIP405_1000" OR "MIP405T_1000" */
595 #if !defined(CONFIG_MIP405T)
596 #define BOARD_NAME "MIP405"
598 #define BOARD_NAME "MIP405T"
601 int checkboard (void)
604 unsigned char bc, var;
606 backup_t *b = (backup_t *) s;
609 get_pcbrev_var(&bc,&var);
610 i = getenv_f("serial#", (char *)s, 32);
611 if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
612 get_backup_values (b);
613 if (strncmp (b->signature, "MPL\0", 4) != 0) {
614 puts ("### No HW ID - assuming " BOARD_NAME);
615 printf ("-%d Rev %c", var, 'A' + bc);
617 b->serial_name[sizeof(BOARD_NAME)-1] = 0;
618 printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
619 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
622 s[sizeof(BOARD_NAME)-1] = 0;
623 printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
624 &s[sizeof(BOARD_NAME)]);
626 bc = in8 (PLD_EXT_CONF_REG);
627 printf (" Boot Config: 0x%x\n", bc);
632 /* ------------------------------------------------------------------------- */
633 /* ------------------------------------------------------------------------- */
635 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
636 the necessary info for SDRAM controller configuration
638 /* ------------------------------------------------------------------------- */
639 /* ------------------------------------------------------------------------- */
640 static int test_dram (unsigned long ramsize);
642 phys_size_t initdram (int board_type)
645 unsigned long bank_reg[4], tmp, bank_size;
647 unsigned long TotalSize;
649 /* since the DRAM controller is allready set up, calculate the size with the
651 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
652 bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
653 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
654 bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
655 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
656 bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
657 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
658 bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
660 for (i = 0; i < 4; i++) {
661 if ((bank_reg[i] & 0x1) == 0x1) {
662 tmp = (bank_reg[i] >> 17) & 0x7;
663 bank_size = 4 << tmp;
664 TotalSize += bank_size;
667 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
668 tmp = mfdcr (SDRAM0_CFGDATA);
674 test_dram (TotalSize * MEGA_BYTE);
675 return (TotalSize * MEGA_BYTE);
678 /* ------------------------------------------------------------------------- */
681 static int test_dram (unsigned long ramsize)
684 mem_test (0L, ramsize, 1);
686 /* not yet implemented */
690 /* used to check if the time in RTC is valid */
691 static unsigned long start;
692 static struct rtc_time tm;
694 int misc_init_r (void)
696 /* adjust flash start and size as well as the offset */
697 gd->bd->bi_flashstart=0-flash_info[0].size;
698 gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
699 gd->bd->bi_flashoffset=0;
701 /* check, if RTC is running */
704 /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
705 if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
706 mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
712 void print_mip405_rev (void)
714 unsigned char part, vers, pcbrev, var;
716 get_pcbrev_var(&pcbrev,&var);
717 part = in8 (PLD_PART_REG);
718 vers = in8 (PLD_VERS_REG);
719 printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
720 var, pcbrev + 'A', part & 0x7F, vers);
724 extern int mk_date (char *, struct rtc_time *);
726 int last_stage_init (void)
729 struct rtc_time newtm;
732 /* write correct LED configuration */
733 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
734 printf ("Error writing to the PHY\n");
736 /* since LED/CFG2 is not connected on the -2,
737 * write to correct capability information */
738 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
739 printf ("Error writing to the PHY\n");
742 stdio_print_current_devices ();
744 /* check if RTC time is valid */
745 stop=get_timer(start);
746 while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */
748 stop=get_timer(start);
751 if(tm.tm_sec==newtm.tm_sec) {
752 s=getenv("defaultdate");
754 mk_date ("010112001970", &newtm);
756 if(mk_date (s, &newtm)!=0) {
757 printf("RTC: Bad date format in defaultdate\n");
766 /***************************************************************************
767 * some helping routines
770 int overwrite_console (void)
772 /* return true if console should be overwritten */
773 return ((in8(PLD_EXT_CONF_REG) & 0x1) == 0);
777 /************************************************************************
779 ************************************************************************/
780 void print_mip405_info (void)
782 unsigned char part, vers, cfg, irq_reg, com_mode, ext;
784 part = in8 (PLD_PART_REG);
785 vers = in8 (PLD_VERS_REG);
786 cfg = in8 (PLD_BOARD_CFG_REG);
787 irq_reg = in8 (PLD_IRQ_REG);
788 com_mode = in8 (PLD_COM_MODE_REG);
789 ext = in8 (PLD_EXT_CONF_REG);
791 printf ("PLD Part %d version %d\n", part & 0x7F, vers);
792 printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
793 printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
794 (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
795 printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
796 printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
797 #if !defined(CONFIG_MIP405T)
798 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
799 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
800 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
801 (ext >> 6) & 0x1, (ext >> 7) & 0x1);
802 printf ("SER1 uses handshakes %s\n",
803 (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
805 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
806 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
807 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
808 (ext >> 6) & 0x1,(ext >> 7) & 0x1);
810 printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
812 printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
813 #if !defined(CONFIG_MIP405T)
814 printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
815 printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
817 printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
818 printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
819 printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");