3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * How do I program the SDRAM Timing Register (SDRAM0_TR) for a specific SDRAM or DIMM?
30 * As an example, consider a case where PC133 memory with CAS Latency equal to 2 is being
31 * used with a 200MHz 405GP. For a typical 128Mb, PC133 SDRAM, the relevant minimum
32 * parameters from the datasheet are:
33 * Tclk = 7.5ns (CL = 2)
39 * If we are operating the 405GP with the MemClk output frequency set to 100 MHZ, the clock
40 * period is 10ns and the parameters needed for the Timing Register are:
41 * CASL = CL = 2 clock cycles
42 * PTA = Trp = 15ns / 10ns = 2 clock cycles
43 * CTP = Trc - Trcd - Trp = (60ns - 15ns - 15ns) / 10ns= 3 clock cycles
44 * LDF = 2 clock cycles (but can be extended to meet board-level timing)
45 * RFTA = Trfc = 66ns / 10ns= 7 clock cycles
46 * RCD = Trcd = 15ns / 10ns= 2 clock cycles
48 * The actual bit settings in the register would be:
57 * If Trfc is not specified in the datasheet for PC100 or PC133 memory, set RFTA = Trc
58 * instead. Figure 24 in the PC SDRAM Specification Rev. 1.7 shows refresh to active delay
59 * defined as Trc rather than Trfc.
60 * When using DIMM modules, most but not all of the required timing parameters can be read
61 * from the Serial Presence Detect (SPD) EEPROM on the module. Specifically, Trc and Trfc
62 * are not available from the EEPROM
67 #include <asm/processor.h>
68 #include <asm/ppc4xx.h>
69 #include <asm/ppc4xx-i2c.h>
71 #include "../common/common_util.h"
72 #include <stdio_dev.h>
76 DECLARE_GLOBAL_DATA_PTR;
79 #define ENABLE_ECC /* for ecc boards */
83 /* stdlib.h causes some compatibility problems; should fixe these! -- wd */
84 #ifndef __ldiv_t_defined
86 long int quot; /* Quotient */
87 long int rem; /* Remainder */
89 extern ldiv_t ldiv (long int __numer, long int __denom);
90 # define __ldiv_t_defined 1
94 #define PLD_PART_REG PER_PLD_ADDR + 0
95 #define PLD_VERS_REG PER_PLD_ADDR + 1
96 #define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
97 #define PLD_IRQ_REG PER_PLD_ADDR + 3
98 #define PLD_COM_MODE_REG PER_PLD_ADDR + 4
99 #define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
101 #define MEGA_BYTE (1024*1024)
104 unsigned char boardtype; /* Board revision and Population Options */
105 unsigned char cal; /* cas Latency (will be programmend as cal-1) */
106 unsigned char trp; /* datain27 in clocks */
107 unsigned char trcd; /* datain29 in clocks */
108 unsigned char tras; /* datain30 in clocks */
109 unsigned char tctp; /* tras - trcd in clocks */
110 unsigned char am; /* Address Mod (will be programmed as am-1) */
111 unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
112 unsigned char ecc; /* if true, ecc is enabled */
114 #if defined(CONFIG_MIP405T)
115 const sdram_t sdram_table[] = {
116 { 0x0F, /* MIP405T Rev A, 64MByte -1 Board */
117 3, /* Case Latenty = 3 */
118 3, /* trp 20ns / 7.5 ns datain[27] */
119 3, /* trcd 20ns /7.5 ns (datain[29]) */
120 6, /* tras 44ns /7.5 ns (datain[30]) */
121 4, /* tcpt 44 - 20ns = 24ns */
122 2, /* Address Mode = 2 (12x9x4) */
123 3, /* size value (32MByte) */
124 0}, /* ECC disabled */
125 { 0xff, /* terminator */
135 const sdram_t sdram_table[] = {
136 { 0x0f, /* Rev A, 128MByte -1 Board */
137 3, /* Case Latenty = 3 */
138 3, /* trp 20ns / 7.5 ns datain[27] */
139 3, /* trcd 20ns /7.5 ns (datain[29]) */
140 6, /* tras 44ns /7.5 ns (datain[30]) */
141 4, /* tcpt 44 - 20ns = 24ns */
142 3, /* Address Mode = 3 */
144 1}, /* ECC enabled */
145 { 0x07, /* Rev A, 64MByte -2 Board */
146 3, /* Case Latenty = 3 */
147 3, /* trp 20ns / 7.5 ns datain[27] */
148 3, /* trcd 20ns /7.5 ns (datain[29]) */
149 6, /* tras 44ns /7.5 ns (datain[30]) */
150 4, /* tcpt 44 - 20ns = 24ns */
151 2, /* Address Mode = 2 */
153 1}, /* ECC enabled */
154 { 0x03, /* Rev A, 128MByte -4 Board */
155 3, /* Case Latenty = 3 */
156 3, /* trp 20ns / 7.5 ns datain[27] */
157 3, /* trcd 20ns /7.5 ns (datain[29]) */
158 6, /* tras 44ns /7.5 ns (datain[30]) */
159 4, /* tcpt 44 - 20ns = 24ns */
160 3, /* Address Mode = 3 */
162 1}, /* ECC enabled */
163 { 0x1f, /* Rev B, 128MByte -3 Board */
164 3, /* Case Latenty = 3 */
165 3, /* trp 20ns / 7.5 ns datain[27] */
166 3, /* trcd 20ns /7.5 ns (datain[29]) */
167 6, /* tras 44ns /7.5 ns (datain[30]) */
168 4, /* tcpt 44 - 20ns = 24ns */
169 3, /* Address Mode = 3 */
171 1}, /* ECC enabled */
172 { 0x2f, /* Rev C, 128MByte -3 Board */
173 3, /* Case Latenty = 3 */
174 3, /* trp 20ns / 7.5 ns datain[27] */
175 3, /* trcd 20ns /7.5 ns (datain[29]) */
176 6, /* tras 44ns /7.5 ns (datain[30]) */
177 4, /* tcpt 44 - 20ns = 24ns */
178 3, /* Address Mode = 3 */
180 1}, /* ECC enabled */
181 { 0xff, /* terminator */
190 #endif /*CONFIG_MIP405T */
191 void SDRAM_err (const char *s)
194 (void) get_clocks ();
200 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
205 unsigned char get_board_revcfg (void)
207 out8 (PER_BOARD_ADDR, 0);
208 return (in8 (PER_BOARD_ADDR));
214 void write_hex (unsigned char i)
221 serial_putc (cc + 55);
223 serial_putc (cc + 48);
226 serial_putc (cc + 55);
228 serial_putc (cc + 48);
231 void write_4hex (unsigned long val)
233 write_hex ((unsigned char) (val >> 24));
234 write_hex ((unsigned char) (val >> 16));
235 write_hex ((unsigned char) (val >> 8));
236 write_hex ((unsigned char) val);
242 int init_sdram (void)
244 unsigned long tmp, baseaddr;
246 unsigned char trp_clocks,
251 unsigned char cal_val;
253 unsigned long sdram_tim, sdram_bank;
255 /*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
256 (void) get_clocks ();
260 mtdcr (EBC0_CFGADDR, PB7AP);
261 mtdcr (EBC0_CFGDATA, PLD_AP);
262 mtdcr (EBC0_CFGADDR, PB7CR);
263 mtdcr (EBC0_CFGDATA, PLD_CR);
264 /* THIS IS OBSOLETE */
265 /* set up the board rev reg*/
266 mtdcr (EBC0_CFGADDR, PB5AP);
267 mtdcr (EBC0_CFGDATA, BOARD_AP);
268 mtdcr (EBC0_CFGADDR, PB5CR);
269 mtdcr (EBC0_CFGDATA, BOARD_CR);
271 /* get all informations from PLD */
272 serial_puts ("\nPLD Part 0x");
273 bc = in8 (PLD_PART_REG);
275 serial_puts ("\nPLD Vers 0x");
276 bc = in8 (PLD_VERS_REG);
278 serial_puts ("\nBoard Rev 0x");
279 bc = in8 (PLD_BOARD_CFG_REG);
284 bc = in8 (PLD_PART_REG);
285 #if defined(CONFIG_MIP405T)
287 SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
289 if((bc & 0x80)==0x80)
290 SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
292 /* set-up the chipselect machine */
293 mtdcr (EBC0_CFGADDR, PB0CR); /* get cs0 config reg */
294 tmp = mfdcr (EBC0_CFGDATA);
295 if ((tmp & 0x00002000) == 0) {
296 /* MPS Boot, set up the flash */
297 mtdcr (EBC0_CFGADDR, PB1AP);
298 mtdcr (EBC0_CFGDATA, FLASH_AP);
299 mtdcr (EBC0_CFGADDR, PB1CR);
300 mtdcr (EBC0_CFGDATA, FLASH_CR);
302 /* Flash boot, set up the MPS */
303 mtdcr (EBC0_CFGADDR, PB1AP);
304 mtdcr (EBC0_CFGDATA, MPS_AP);
305 mtdcr (EBC0_CFGADDR, PB1CR);
306 mtdcr (EBC0_CFGDATA, MPS_CR);
308 /* set up UART0 (CS2) and UART1 (CS3) */
309 mtdcr (EBC0_CFGADDR, PB2AP);
310 mtdcr (EBC0_CFGDATA, UART0_AP);
311 mtdcr (EBC0_CFGADDR, PB2CR);
312 mtdcr (EBC0_CFGDATA, UART0_CR);
313 mtdcr (EBC0_CFGADDR, PB3AP);
314 mtdcr (EBC0_CFGDATA, UART1_AP);
315 mtdcr (EBC0_CFGADDR, PB3CR);
316 mtdcr (EBC0_CFGDATA, UART1_CR);
317 bc = in8 (PLD_BOARD_CFG_REG);
319 serial_puts ("\nstart SDRAM Setup\n");
320 serial_puts ("\nBoard Rev: ");
325 baseaddr = CONFIG_SYS_SDRAM_BASE;
326 while (sdram_table[i].sz != 0xff) {
327 if (sdram_table[i].boardtype == bc)
331 if (sdram_table[i].boardtype != bc)
332 SDRAM_err ("No SDRAM table found for this board!!!\n");
334 serial_puts (" found table ");
338 /* since the ECC initialisation needs some time,
339 * we show that we're alive
341 if (sdram_table[i].ecc)
342 serial_puts ("\nInitializing SDRAM, Please stand by");
343 cal_val = sdram_table[i].cal - 1; /* Cas Latency */
344 trp_clocks = sdram_table[i].trp; /* 20ns / 7.5 ns datain[27] */
345 trcd_clocks = sdram_table[i].trcd; /* 20ns /7.5 ns (datain[29]) */
346 tras_clocks = sdram_table[i].tras; /* 44ns /7.5 ns (datain[30]) */
347 /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */
348 tctp_clocks = sdram_table[i].tctp; /* 44 - 20ns = 24ns */
349 /* trc_clocks is sum of trp_clocks + tras_clocks */
350 trc_clocks = trp_clocks + tras_clocks;
351 /* get SDRAM timing register */
352 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
353 sdram_tim = mfdcr (SDRAM0_CFGDATA) & ~0x018FC01F;
354 /* insert CASL value */
355 sdram_tim |= ((unsigned long) (cal_val)) << 23;
356 /* insert PTA value */
357 sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
358 /* insert CTP value */
360 ((unsigned long) (trc_clocks - trp_clocks -
362 /* insert LDF (always 01) */
363 sdram_tim |= ((unsigned long) 0x01) << 14;
364 /* insert RFTA value */
365 sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
366 /* insert RCD value */
367 sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
369 tmp = ((unsigned long) (sdram_table[i].am - 1) << 13); /* AM = 3 */
370 /* insert SZ value; */
371 tmp |= ((unsigned long) sdram_table[i].sz << 17);
372 /* get SDRAM bank 0 register */
373 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
374 sdram_bank = mfdcr (SDRAM0_CFGDATA) & ~0xFFCEE001;
375 sdram_bank |= (baseaddr | tmp | 0x01);
378 serial_puts ("sdtr: ");
379 write_4hex (sdram_tim);
383 /* write SDRAM timing register */
384 mtdcr (SDRAM0_CFGADDR, SDRAM0_TR);
385 mtdcr (SDRAM0_CFGDATA, sdram_tim);
388 serial_puts ("mb0cf: ");
389 write_4hex (sdram_bank);
393 /* write SDRAM bank 0 register */
394 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
395 mtdcr (SDRAM0_CFGDATA, sdram_bank);
397 if (get_bus_freq (tmp) > 110000000) { /* > 110MHz */
398 /* get SDRAM refresh interval register */
399 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
400 tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
403 /* get SDRAM refresh interval register */
404 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
405 tmp = mfdcr (SDRAM0_CFGDATA) & ~0x3FF80000;
408 /* write SDRAM refresh interval register */
409 mtdcr (SDRAM0_CFGADDR, SDRAM0_RTR);
410 mtdcr (SDRAM0_CFGDATA, tmp);
411 /* enable ECC if used */
412 #if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
413 if (sdram_table[i].ecc) {
414 /* disable checking for all banks */
417 serial_puts ("disable ECC.. ");
419 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
420 tmp = mfdcr (SDRAM0_CFGDATA);
421 tmp &= 0xff0fffff; /* disable all banks */
422 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
423 /* set up SDRAM Controller with ECC enabled */
425 serial_puts ("setup SDRAM Controller.. ");
427 mtdcr (SDRAM0_CFGDATA, tmp);
428 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
429 tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x90800000;
430 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
431 mtdcr (SDRAM0_CFGDATA, tmp);
434 serial_puts ("fill the memory..\n");
437 /* now, fill all the memory */
438 tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
439 p = (unsigned long) 0;
440 while ((unsigned long) p < tmp) {
442 if (!((unsigned long) p % 0x00800000)) /* every 8MByte */
448 serial_puts ("enable ECC\n");
451 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
452 tmp = mfdcr (SDRAM0_CFGDATA);
453 tmp |= 0x00800000; /* enable bank 0 */
454 mtdcr (SDRAM0_CFGDATA, tmp);
459 /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */
460 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
461 tmp = (mfdcr (SDRAM0_CFGDATA) & ~0xFFE00000) | 0x80C00000;
462 mtdcr (SDRAM0_CFGADDR, SDRAM0_CFG);
463 mtdcr (SDRAM0_CFGDATA, tmp);
470 int board_early_init_f (void)
474 /*-------------------------------------------------------------------------+
475 | Interrupt controller setup for the PIP405 board.
476 | Note: IRQ 0-15 405GP internally generated; active high; level sensitive
477 | IRQ 16 405GP internally generated; active low; level sensitive
479 | IRQ 25 (EXT IRQ 0) SouthBridge; active low; level sensitive
480 | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive
481 | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive
482 | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
483 | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
484 | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
485 | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
486 | Note for MIP405 board:
487 | An interrupt taken for the SouthBridge (IRQ 25) indicates that
488 | the Interrupt Controller in the South Bridge has caused the
489 | interrupt. The IC must be read to determine which device
490 | caused the interrupt.
492 +-------------------------------------------------------------------------*/
493 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
494 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
495 mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical (for now) */
496 mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */
497 mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */
498 mtdcr (UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
499 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
505 * Get some PLD Registers
508 unsigned short get_pld_parvers (void)
510 unsigned short result;
513 rc = in8 (PLD_PART_REG);
514 result = (unsigned short) rc << 8;
515 rc = in8 (PLD_VERS_REG);
521 void user_led0 (unsigned char on)
524 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
526 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
530 void ide_set_reset (int idereset)
532 /* if reset = 1 IDE reset will be asserted */
534 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
537 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
542 /* ------------------------------------------------------------------------- */
544 void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
546 #if !defined(CONFIG_MIP405T)
547 unsigned char bc,rc,tmp;
550 bc = in8 (PLD_BOARD_CFG_REG);
554 for (i = 0; i < 4; i++) {
560 if(( (((bc>>4) & 0xf)==0x2) /* Rev C PCB or */
561 || (((bc>>4) & 0xf)==0x1)) /* Rev B PCB with */
562 && (rc==0x1)) /* Population Option 1 is a -3 */
564 *pcbrev=(bc >> 4) & 0xf;
568 bc = in8 (PLD_BOARD_CFG_REG);
569 *pcbrev=(bc >> 4) & 0xf;
575 * Check Board Identity:
577 /* serial String: "MIP405_1000" OR "MIP405T_1000" */
578 #if !defined(CONFIG_MIP405T)
579 #define BOARD_NAME "MIP405"
581 #define BOARD_NAME "MIP405T"
584 int checkboard (void)
587 unsigned char bc, var;
589 backup_t *b = (backup_t *) s;
592 get_pcbrev_var(&bc,&var);
593 i = getenv_f("serial#", (char *)s, 32);
594 if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
595 get_backup_values (b);
596 if (strncmp (b->signature, "MPL\0", 4) != 0) {
597 puts ("### No HW ID - assuming " BOARD_NAME);
598 printf ("-%d Rev %c", var, 'A' + bc);
600 b->serial_name[sizeof(BOARD_NAME)-1] = 0;
601 printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
602 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
605 s[sizeof(BOARD_NAME)-1] = 0;
606 printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
607 &s[sizeof(BOARD_NAME)]);
609 bc = in8 (PLD_EXT_CONF_REG);
610 printf (" Boot Config: 0x%x\n", bc);
615 /* ------------------------------------------------------------------------- */
616 /* ------------------------------------------------------------------------- */
618 initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
619 the necessary info for SDRAM controller configuration
621 /* ------------------------------------------------------------------------- */
622 /* ------------------------------------------------------------------------- */
623 static int test_dram (unsigned long ramsize);
625 phys_size_t initdram (int board_type)
628 unsigned long bank_reg[4], tmp, bank_size;
630 unsigned long TotalSize;
633 /* since the DRAM controller is allready set up, calculate the size with the
635 mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
636 bank_reg[0] = mfdcr (SDRAM0_CFGDATA);
637 mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
638 bank_reg[1] = mfdcr (SDRAM0_CFGDATA);
639 mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
640 bank_reg[2] = mfdcr (SDRAM0_CFGDATA);
641 mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
642 bank_reg[3] = mfdcr (SDRAM0_CFGDATA);
644 for (i = 0; i < 4; i++) {
645 if ((bank_reg[i] & 0x1) == 0x1) {
646 tmp = (bank_reg[i] >> 17) & 0x7;
647 bank_size = 4 << tmp;
648 TotalSize += bank_size;
652 mtdcr (SDRAM0_CFGADDR, SDRAM0_ECCCFG);
653 tmp = mfdcr (SDRAM0_CFGDATA);
659 test_dram (TotalSize * MEGA_BYTE);
660 return (TotalSize * MEGA_BYTE);
663 /* ------------------------------------------------------------------------- */
666 static int test_dram (unsigned long ramsize)
669 mem_test (0L, ramsize, 1);
671 /* not yet implemented */
675 /* used to check if the time in RTC is valid */
676 static unsigned long start;
677 static struct rtc_time tm;
678 extern flash_info_t flash_info[]; /* info for FLASH chips */
680 int misc_init_r (void)
682 /* adjust flash start and size as well as the offset */
683 gd->bd->bi_flashstart=0-flash_info[0].size;
684 gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
685 gd->bd->bi_flashoffset=0;
687 /* check, if RTC is running */
690 /* if MIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
691 if (mfdcr(CPC0_PSR) & PSR_ROM_LOC)
692 mtspr(SPRN_CCR0, (mfspr(SPRN_CCR0) & ~0x80));
698 void print_mip405_rev (void)
700 unsigned char part, vers, pcbrev, var;
702 get_pcbrev_var(&pcbrev,&var);
703 part = in8 (PLD_PART_REG);
704 vers = in8 (PLD_VERS_REG);
705 printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
706 var, pcbrev + 'A', part & 0x7F, vers);
710 extern int mk_date (char *, struct rtc_time *);
712 int last_stage_init (void)
715 struct rtc_time newtm;
718 /* write correct LED configuration */
719 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
720 printf ("Error writing to the PHY\n");
722 /* since LED/CFG2 is not connected on the -2,
723 * write to correct capability information */
724 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
725 printf ("Error writing to the PHY\n");
728 stdio_print_current_devices ();
730 /* check if RTC time is valid */
731 stop=get_timer(start);
732 while(stop<1200) { /* we wait 1.2 sec to check if the RTC is running */
734 stop=get_timer(start);
737 if(tm.tm_sec==newtm.tm_sec) {
738 s=getenv("defaultdate");
740 mk_date ("010112001970", &newtm);
742 if(mk_date (s, &newtm)!=0) {
743 printf("RTC: Bad date format in defaultdate\n");
752 /***************************************************************************
753 * some helping routines
756 int overwrite_console (void)
758 return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0); /* return TRUE if console should be overwritten */
762 /************************************************************************
764 ************************************************************************/
765 void print_mip405_info (void)
767 unsigned char part, vers, cfg, irq_reg, com_mode, ext;
769 part = in8 (PLD_PART_REG);
770 vers = in8 (PLD_VERS_REG);
771 cfg = in8 (PLD_BOARD_CFG_REG);
772 irq_reg = in8 (PLD_IRQ_REG);
773 com_mode = in8 (PLD_COM_MODE_REG);
774 ext = in8 (PLD_EXT_CONF_REG);
776 printf ("PLD Part %d version %d\n", part & 0x7F, vers);
777 printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
778 printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
779 (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
780 printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
781 printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
782 #if !defined(CONFIG_MIP405T)
783 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
784 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
785 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
786 (ext >> 6) & 0x1, (ext >> 7) & 0x1);
787 printf ("SER1 uses handshakes %s\n",
788 (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
790 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
791 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
792 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
793 (ext >> 6) & 0x1,(ext >> 7) & 0x1);
795 printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
797 printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
798 #if !defined(CONFIG_MIP405T)
799 printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
800 printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
802 printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
803 printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
804 printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");