3 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
5 * SPDX-License-Identifier: GPL-2.0+
7 /****************************************************************************
8 * Global routines used for MIP405
9 *****************************************************************************/
11 /*int switch_cs(unsigned char boot);*/
13 extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
15 void user_led0(unsigned char on);
21 #define PLD_BME 0 /* Burst disable */
22 #define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
23 #define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
24 #define PLD_OEN 1 /* Cycles from CS low to OE low */
25 #define PLD_WBN 1 /* Cycles from CS low to WE low */
26 #define PLD_WBF 1 /* Cycles from WE high to CS high */
27 #define PLD_TH 2 /* Number of hold cycles after transfer */
28 #define PLD_RE 0 /* Ready disabled */
29 #define PLD_SOR 1 /* Sample on Ready disabled */
30 #define PLD_BEM 0 /* Byte Write only active on Write cycles */
31 #define PLD_PEN 0 /* Parity disable */
32 #define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
33 (PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
35 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
36 #define PLD_BS 0 /* 1 MByte */
37 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
38 #define PLD_BU 3 /* R/W */
39 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
40 #define PLD_BW 0 /* 16Bit */
41 #define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
46 #define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
47 /* Dummy CS to get the board revision */
48 #define BOARD_BME 0 /* Burst disable */
49 #define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
50 #define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
51 #define BOARD_OEN 1 /* Cycles from CS low to OE low */
52 #define BOARD_WBN 1 /* Cycles from CS low to WE low */
53 #define BOARD_WBF 1 /* Cycles from WE high to CS high */
54 #define BOARD_TH 2 /* Number of hold cycles after transfer */
55 #define BOARD_RE 0 /* Ready disabled */
56 #define BOARD_SOR 1 /* Sample on Ready disabled */
57 #define BOARD_BEM 0 /* Byte Write only active on Write cycles */
58 #define BOARD_PEN 0 /* Parity disable */
59 #define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
60 (BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
62 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
63 #define BOARD_BS 0 /* 1 MByte */
64 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
65 #define BOARD_BU 3 /* R/W */
66 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
67 #define BOARD_BW 0 /* 16Bit */
68 #define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
72 #define UART0_BME 0 /* Burst disable */
73 #define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
74 #define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
75 #define UART0_OEN 1 /* Cycles from CS low to OE low */
76 #define UART0_WBN 1 /* Cycles from CS low to WE low */
77 #define UART0_WBF 1 /* Cycles from WE high to CS high */
78 #define UART0_TH 2 /* Number of hold cycles after transfer */
79 #define UART0_RE 0 /* Ready disabled */
80 #define UART0_SOR 1 /* Sample on Ready disabled */
81 #define UART0_BEM 0 /* Byte Write only active on Write cycles */
82 #define UART0_PEN 0 /* Parity disable */
83 #define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
84 (UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
86 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
87 #define UART0_BS 0 /* 1 MByte */
88 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
89 #define UART0_BU 3 /* R/W */
90 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
91 #define UART0_BW 0 /* 8Bit */
92 #define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
95 #define UART1_AP UART0_AP /* same timing as UART0 */
96 #define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
99 /* Flash CS0 or CS 1 */
100 /* 0x7F8FFE80 slowest timing at all... */
101 #define FLASH_BME_B 1 /* Burst enable */
102 #define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
103 #define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
104 #define FLASH_BME 0 /* Burst disable */
105 #define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
106 #define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
107 #define FLASH_OEN 1 /* Cycles from CS low to OE low */
108 #define FLASH_WBN 1 /* Cycles from CS low to WE low */
109 #define FLASH_WBF 1 /* Cycles from WE high to CS high */
110 #define FLASH_TH 2 /* Number of hold cycles after transfer */
111 #define FLASH_RE 0 /* Ready disabled */
112 #define FLASH_SOR 1 /* Sample on Ready disabled */
113 #define FLASH_BEM 0 /* Byte Write only active on Write cycles */
114 #define FLASH_PEN 0 /* Parity disable */
115 /* Access Parameter Register for non Boot */
116 #define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
117 (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
118 /* Access Parameter Register for Boot */
119 #define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
120 (FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
122 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
123 #define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
124 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
125 #define FLASH_BU 3 /* R/W */
126 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
127 #define FLASH_BW 1 /* 16Bit */
128 /* CR register for Boot */
129 #define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
130 /* CR register for non Boot */
131 #define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
135 #define MPS_BME_B 1 /* Burst enable */
136 #define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
137 #define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
138 #define MPS_BME 0 /* Burst disable */
139 #define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
140 #define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
141 #define MPS_OEN 1 /* Cycles from CS low to OE low */
142 #define MPS_WBN 1 /* Cycles from CS low to WE low */
143 #define MPS_WBF 1 /* Cycles from WE high to CS high */
144 #define MPS_TH 2 /* Number of hold cycles after transfer */
145 #define MPS_RE 0 /* Ready disabled */
146 #define MPS_SOR 1 /* Sample on Ready disabled */
147 #define MPS_BEM 0 /* Byte Write only active on Write cycles */
148 #define MPS_PEN 0 /* Parity disable */
149 /* Access Parameter Register for non Boot */
150 #define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
151 (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
152 /* Access Parameter Register for Boot */
153 #define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
154 (MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
156 /* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
157 #define MPS_BS 2 /* 4 MByte */
158 #define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
159 /* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
160 #define MPS_BU 3 /* R/W */
161 /* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
162 #define MPS_BW 0 /* 8Bit */
163 /* CR register for Boot */
164 #define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
165 /* CR register for non Boot */
166 #define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))