3 * Martin Winistoerfer, martinwinistoerfer@gmx.ch.
5 * Denis Peter, d.peter@mpl.ch
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 /***********************************************************************************
26 * Bits for the SDRAM controller
27 * -----------------------------
29 * CAL: CAS Latency. If cleared to 0 (default) the SDRAM controller asserts TA# on
30 * the 2nd Clock after ACTIVE command (CAS Latency = 2). If set to 1 the SDRAM
31 * controller asserts TA# on the 3rd Clock after ACTIVE command (CAS Latency = 3).
32 * RCD: RCD ACTIVE to READ or WRITE Delay (Ras to Cas Delay). If cleared 0 (default)
33 * tRCD of the SDRAM must equal or less 25ns. If set to 1 tRCD must be equal or less 50ns.
34 * WREC:Write Recovery. If cleared 0 (default) tWR of the SDRAM must equal or less 25ns.
35 * If set to 1 tWR must be equal or less 50ns.
36 * RP: Precharge Command Time. If cleared 0 (default) tRP of the SDRAM must equal or less
37 * 25ns. If set to 1 tRP must be equal or less 50ns.
38 * RC: Auto Refresh to Active Time. If cleared 0 (default) tRC of the SDRAM must equal
39 * or less 75ns. If set to 1 tRC must be equal or less 100ns.
40 * LMR: Bit to set the Mode Register of the SDRAM. If set, the next access to the SDRAM
41 * is the Load Mode Register Command.
42 * IIP: Init in progress. Set to 1 for starting the init sequence
43 * (Precharge All). As long this bit is set, the Precharge All is still in progress.
44 * After command has completed, wait at least for 8 refresh (200usec) before proceed.
45 **********************************************************************************/
49 #include <stdio_dev.h>
55 #if defined(__APPLE__)
56 /* Leading underscore on symbols */
58 #else /* No leading character on symbols */
64 * Macros to generate global absolutes.
66 #define GEN_SYMNAME(str) SYM_CHAR #str
67 #define GEN_VALUE(str) #str
68 #define GEN_ABS(name, value) \
69 asm (".globl " GEN_SYMNAME(name)); \
70 asm (GEN_SYMNAME(name) " = " GEN_VALUE(value))
73 /************************************************************************
74 * Early debug routines
76 void write_hex (unsigned char i)
83 serial_putc (cc + 55);
85 serial_putc (cc + 48);
88 serial_putc (cc + 55);
90 serial_putc (cc + 48);
93 #if defined(SDRAM_DEBUG)
95 void write_4hex (unsigned long val)
97 write_hex ((unsigned char) (val >> 24));
98 write_hex ((unsigned char) (val >> 16));
99 write_hex ((unsigned char) (val >> 8));
100 write_hex ((unsigned char) val);
105 unsigned long in32(unsigned long addr)
107 unsigned long *p=(unsigned long *)addr;
111 void out32(unsigned long addr,unsigned long data)
113 unsigned long *p=(unsigned long *)addr;
118 unsigned short boardtype; /* Board revision and Population Options */
119 unsigned char cal; /* cas Latency 0:CAL=2 1:CAL=3 */
120 unsigned char rcd; /* ras to cas delay 0:<25ns 1:<50ns*/
121 unsigned char wrec; /* write recovery 0:<25ns 1:<50ns */
122 unsigned char pr; /* Precharge Command Time 0:<25ns 1:<50ns */
123 unsigned char rc; /* Auto Refresh to Active Time 0:<75ns 1:<100ns */
124 unsigned char sz; /* log binary => Size = (4MByte<<sz) 5 = 128, 4 = 64, 3 = 32, 2 = 16, 1=8 */
127 const sdram_t sdram_table[] = {
128 { 0x0000, /* PATI Rev A, 16MByte -1 Board */
129 1, /* Case Latenty = 3 */
130 0, /* ras to cas delay 0 (20ns) */
131 0, /* write recovery 0:<25ns 1:<50ns*/
132 0, /* Precharge Command Time 0 (20ns) */
133 0, /* Auto Refresh to Active Time 0 (68) */
134 2 /* log binary => Size 2 = 16MByte, 1=8 */
136 { 0xffff, /* terminator */
146 extern int mem_test (unsigned long start, unsigned long ramsize, int quiet);
151 phys_size_t initdram(int board_type)
153 unsigned char board_rev;
158 #if defined(SDRAM_DEBUG)
159 reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
160 puts("\n\nSYSTEM part 0x"); write_4hex(SYSCNTR_PART(reg));
161 puts(" Vers 0x"); write_4hex(SYSCNTR_ID(reg));
162 puts("\nSDRAM part 0x"); write_4hex(SDRAM_PART(reg));
163 puts(" Vers 0x"); write_4hex(SDRAM_ID(reg));
164 reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
165 puts("\nBoard rev. 0x"); write_4hex(SYSCNTR_BREV(reg));
168 reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
169 board_rev=(unsigned char)(SYSCNTR_BREV(reg));
172 if(sdram_table[i].boardtype==0xffff) {
173 puts("ERROR, found no table for Board 0x");
174 write_hex(board_rev);
177 if(sdram_table[i].boardtype==(unsigned char)board_rev)
181 /* Set CAL, RCD, WREQ, PR and RC Bits */
182 #if defined(SDRAM_DEBUG)
183 puts("Set CAL, RCD, WREQ, PR and RC Bits\n");
186 reg &= ~(SET_REG_BIT(1,SDRAM_CAL) | SET_REG_BIT(1,SDRAM_RCD) | SET_REG_BIT(1,SDRAM_WREQ) |
187 SET_REG_BIT(1,SDRAM_PR) | SET_REG_BIT(1,SDRAM_RC) | SET_REG_BIT(1,SDRAM_LMR) |
188 SET_REG_BIT(1,SDRAM_IIP) | SET_REG_BIT(1,SDRAM_RES0));
190 reg |= (SET_REG_BIT(sdram_table[i].cal,SDRAM_CAL) |
191 SET_REG_BIT(sdram_table[i].rcd,SDRAM_RCD) |
192 SET_REG_BIT(sdram_table[i].wrec,SDRAM_WREQ) |
193 SET_REG_BIT(sdram_table[i].pr,SDRAM_PR) |
194 SET_REG_BIT(sdram_table[i].rc,SDRAM_RC));
196 out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
198 #if defined(SDRAM_DEBUG)
199 puts("step 2 set IIP\n");
202 reg |= SET_REG_BIT(1,SDRAM_IIP);
204 while (timeout!=0xffff) {
205 __asm__ volatile("eieio");
206 reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
207 if((reg & SET_REG_BIT(1,SDRAM_IIP))==0)
212 /* wait for at least 8 refresh */
215 reg |= SET_REG_BIT(1,SDRAM_LMR);
216 out32(PLD_CONFIG_BASE+PLD_BOARD_TIMING,reg);
217 __asm__ volatile("eieio");
218 lmr=0x00000002; /* sequential burst 4 data */
219 if(sdram_table[i].cal==1)
220 lmr|=0x00000030; /* cal = 3 */
222 lmr|=0000000020; /* cal = 2 */
223 /* rest standard operation programmed write burst length */
224 /* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
226 in32(CONFIG_SYS_SDRAM_BASE + lmr);
227 /* ok, we're done, return SDRAM size */
228 return ((0x400000 << sdram_table[i].sz)); /* log2 value of 4MByte */
232 void set_flash_vpp(int ext_vpp, int ext_wp, int int_vpp)
235 reg=in32(PLD_CONF_REG2+PLD_CONFIG_BASE);
236 reg &= ~(SET_REG_BIT(1,SYSCNTR_CPU_VPP) |
237 SET_REG_BIT(1,SYSCNTR_FL_VPP) |
238 SET_REG_BIT(1,SYSCNTR_FL_WP));
240 reg |= (SET_REG_BIT(int_vpp,SYSCNTR_CPU_VPP) |
241 SET_REG_BIT(ext_vpp,SYSCNTR_FL_VPP) |
242 SET_REG_BIT(ext_wp,SYSCNTR_FL_WP));
243 out32(PLD_CONF_REG2+PLD_CONFIG_BASE,reg);
248 void show_pld_regs(void)
250 unsigned long reg,reg1;
251 reg=in32(PLD_CONFIG_BASE+PLD_PART_ID);
252 printf("\nSYSTEM part %ld, Vers %ld\n",SYSCNTR_PART(reg),SYSCNTR_ID(reg));
253 printf("SDRAM part %ld, Vers %ld\n",SDRAM_PART(reg),SDRAM_ID(reg));
254 reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
255 printf("Board rev. %c\n",(char) (SYSCNTR_BREV(reg)+'A'));
256 printf("Waitstates %ld\n",GET_SYSCNTR_FLWAIT(reg));
257 printf("SDRAM: CAL=%ld RCD=%ld WREQ=%ld PR=%ld\n RC=%ld LMR=%ld IIP=%ld\n",
258 GET_REG_BIT(reg,SDRAM_CAL),GET_REG_BIT(reg,SDRAM_RCD),
259 GET_REG_BIT(reg,SDRAM_WREQ),GET_REG_BIT(reg,SDRAM_PR),
260 GET_REG_BIT(reg,SDRAM_RC),GET_REG_BIT(reg,SDRAM_LMR),
261 GET_REG_BIT(reg,SDRAM_IIP));
262 reg=in32(PLD_CONFIG_BASE+PLD_CONF_REG1);
263 reg1=in32(PLD_CONFIG_BASE+PLD_CONF_REG2);
264 printf("HW Config: FLAG=%ld IP=%ld index=%ld PRPM=%ld\n ICW=%ld ISB=%ld BDIS=%ld PCIM=%ld\n",
265 GET_REG_BIT(reg,SYSCNTR_FLAG),GET_REG_BIT(reg,SYSCNTR_IP),
266 GET_SYSCNTR_BOOTIND(reg),GET_REG_BIT(reg,SYSCNTR_PRM),
267 GET_REG_BIT(reg,SYSCNTR_ICW),GET_SYSCNTR_ISB(reg),
268 GET_REG_BIT(reg1,SYSCNTR_BDIS),GET_REG_BIT(reg1,SYSCNTR_PCIM));
269 printf("Switches: MUX=%ld PCI_DIS=%ld Boot_EN=%ld Config=%ld\n",GET_SDRAM_MUX(reg),
270 GET_REG_BIT(reg,SDRAM_PDIS),GET_REG_BIT(reg1,SYSCNTR_BOOTEN),
271 GET_SYSCNTR_CFG(reg1));
272 printf("Misc: RIP=%ld CPU_VPP=%ld FLSH_VPP=%ld FLSH_WP=%ld\n\n",
273 GET_REG_BIT(reg,SDRAM_RIP),GET_REG_BIT(reg1,SYSCNTR_CPU_VPP),
274 GET_REG_BIT(reg1,SYSCNTR_FL_VPP),GET_REG_BIT(reg1,SYSCNTR_FL_WP));
278 /****************************************************************
282 * GPIO7 is Interrupt PLX (Output)
284 * GPIO2 is PLX USERi (Output)
285 * GPIO1 is PLX Interrupt (Input)
286 ****************************************************************/
289 volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
290 volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
292 reg=sysconf->sc_sgpiocr; /* Data direction register */
294 reg |= 0x27000000; /* set outpupts */
295 sysconf->sc_sgpiocr=reg; /* Data direction register */
296 reg=sysconf->sc_sgpiodt2; /* Data register */
297 /* set output to 0 */
299 /* set IRQ and USERi to 1 */
301 sysconf->sc_sgpiodt2=reg; /* Data register */
304 void user_led0(int led_on)
306 volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
307 volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
309 reg=sysconf->sc_sgpiodt2; /* Data register */
310 if(led_on) /* set output to 1 */
314 sysconf->sc_sgpiodt2=reg; /* Data register */
317 void user_led1(int led_on)
319 volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
320 volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
322 reg=sysconf->sc_sgpiodt2; /* Data register */
323 if(led_on) /* set output to 1 */
327 sysconf->sc_sgpiodt2=reg; /* Data register */
331 /****************************************************************
333 ****************************************************************/
334 int last_stage_init (void)
340 /****************************************************************
342 ****************************************************************/
344 #define BOARD_NAME "PATI"
346 int checkboard (void)
354 reg=in32(PLD_CONFIG_BASE+PLD_BOARD_TIMING);
355 rev=(char)(SYSCNTR_BREV(reg)+'A');
356 i = getenv_r ("serial#", s, 32);
358 puts ("### No HW ID - assuming " BOARD_NAME);
359 printf(" Rev. %c\n",rev);
362 s[sizeof(BOARD_NAME)-1] = 0;
363 printf ("%s-1 Rev %c SN: %s\n", s,rev,
364 &s[sizeof(BOARD_NAME)]);
366 set_flash_vpp(1,0,0); /* set Flash VPP */
371 #ifdef CONFIG_SYS_PCI_CON_DEVICE
372 /************************************************************************
377 * PCI Host sends message ALIVE, Local acknowledges with ALIVE
379 * PCI_CON console over PCI:
380 * -------------------------
382 * - uses PCI9056_LOC_TO_PCI_DBELL register to signal that
383 * data is avaible (PCIMSG_CONN)
384 * - uses PCI9056_MAILBOX1 to send data
385 * - uses PCI9056_MAILBOX0 to receive data
387 * - uses PCI9056_PCI_TO_LOC_DBELL register to signal that
388 * data is avaible (PCIMSG_CONN)
389 * - uses PCI9056_MAILBOX0 to send data
390 * - uses PCI9056_MAILBOX1 to receive data
394 * - check if PCICON_TRANSMIT_REG is empty
395 * - write data or'ed with 0x80000000 into the PCICON_TRANSMIT_REG
396 * - write PCIMSG_CONN into the PCICON_DBELL_REG to signal a data
399 * - get an interrupt via the PCICON_ACK_REG register message
401 * - write the data from the PCICON_RECEIVE_REG into the receive
402 * buffer and if the receive buffer is not full, clear the
403 * PCICON_RECEIVE_REG (this allows the counterpart to write more data)
404 * - Clear the interrupt by writing 0xFFFFFFFF to the PCICON_ACK_REG
406 * The PCICON_RECEIVE_REG must be cleared by the routine which reads
407 * the receive buffer if the buffer is not full any more
414 #define PCI_CON_PRINTF(fmt,args...) serial_printf (fmt ,##args)
416 #define PCI_CON_PRINTF(fmt,args...)
420 /*********************************************************
421 * we work only with a receive buffer on eiter side.
422 * Transmit buffer is free, if mailbox is cleared.
423 * Transmit character is or'ed with 0x80000000
424 * PATI receive register MAILBOX0
425 * PATI transmit register MAILBOX1
426 *********************************************************/
427 #define PCICON_RECEIVE_REG PCI9056_MAILBOX0
428 #define PCICON_TRANSMIT_REG PCI9056_MAILBOX1
429 #define PCICON_DBELL_REG PCI9056_LOC_TO_PCI_DBELL
430 #define PCICON_ACK_REG PCI9056_PCI_TO_LOC_DBELL
433 #define PCIMSG_ALIVE 0x1
434 #define PCIMSG_CONN 0x2
435 #define PCIMSG_DISC 0x3
436 #define PCIMSG_CON_DATA 0x5
439 #define PCICON_GET_REG(x) (in32(x + PCI_CONFIG_BASE))
440 #define PCICON_SET_REG(x,y) (out32(x + PCI_CONFIG_BASE,y))
441 #define PCICON_TX_FLAG 0x80000000
444 #define REC_BUFFER_SIZE 0x100
445 int recbuf[REC_BUFFER_SIZE];
446 static int r_ptr = 0;
448 struct stdio_dev pci_con_dev;
452 void pci_con_put_it(const char c)
454 /* Test for completition */
457 reg=PCICON_GET_REG(PCICON_TRANSMIT_REG);
459 reg=PCICON_TX_FLAG + c;
460 PCICON_SET_REG(PCICON_TRANSMIT_REG,reg);
461 PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_CON_DATA);
464 void pci_con_putc(const char c)
468 pci_con_put_it('\r');
472 int pci_con_getc(void)
476 while(r_ptr==(volatile int)w_ptr);
478 if(r_ptr==REC_BUFFER_SIZE)
481 diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
484 if((diff<(REC_BUFFER_SIZE-4)) && buff_full) {
487 PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
492 int pci_con_tstc(void)
494 if(r_ptr==(volatile int)w_ptr)
499 void pci_con_puts (const char *s)
507 void pci_con_init (void)
511 PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
515 /*******************************************
517 ******************************************/
518 int pci_dorbell_irq(void)
520 unsigned long reg,data;
522 reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
523 PCI_CON_PRINTF(" PCI9056_INT_CTRL_STAT = %08lX\n",reg);
526 reg=PCICON_GET_REG(PCICON_ACK_REG);
529 PCI_CON_PRINTF(" Alive\n");
530 PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_ALIVE);
533 PCI_CON_PRINTF(" Conn %d",conn);
537 PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
539 PCI_CON_PRINTF(" ... %d\n",conn);
541 case PCIMSG_CON_DATA:
542 data=PCICON_GET_REG(PCICON_RECEIVE_REG);
543 recbuf[w_ptr++]=(int)(data&0xff);
544 PCI_CON_PRINTF(" Data Console %lX, %X %d %d %X\n",data,((int)(data&0xFF)),
545 r_ptr,w_ptr,recbuf[w_ptr-1]);
546 if(w_ptr==REC_BUFFER_SIZE)
549 diff=r_ptr+REC_BUFFER_SIZE-w_ptr;
552 if(diff>(REC_BUFFER_SIZE-4))
556 PCICON_SET_REG(PCICON_RECEIVE_REG,0L);
559 serial_printf(" PCI9056_PCI_TO_LOC_DBELL = %08lX\n",reg);
562 PCICON_SET_REG(PCICON_ACK_REG,~0L);
567 void pci_con_connect(void)
571 reg=PCICON_GET_REG(PCI9056_INT_CTRL_STAT);
572 /* default 0x0f010180 */
574 reg |= 0x00030000; /* enable local dorbell */
575 reg |= 0x00000300; /* enable PCI dorbell */
576 PCICON_SET_REG(PCI9056_INT_CTRL_STAT , reg);
577 irq_install_handler (0x2, (interrupt_handler_t *) pci_dorbell_irq,NULL);
578 memset (&pci_con_dev, 0, sizeof (pci_con_dev));
579 strcpy (pci_con_dev.name, "pci_con");
580 pci_con_dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
581 pci_con_dev.putc = pci_con_putc;
582 pci_con_dev.puts = pci_con_puts;
583 pci_con_dev.getc = pci_con_getc;
584 pci_con_dev.tstc = pci_con_tstc;
585 stdio_register (&pci_con_dev);
586 printf("PATI ready for PCI connection, type ctrl-c for exit\n");
589 if((volatile int)conn)
592 irq_free_handler(0x2);
596 console_assign(stdin,"pci_con");
597 console_assign(stderr,"pci_con");
598 console_assign(stdout,"pci_con");
601 void pci_con_disc(void)
603 console_assign(stdin,"serial");
604 console_assign(stderr,"serial");
605 console_assign(stdout,"serial");
606 PCICON_SET_REG(PCICON_DBELL_REG,PCIMSG_DISC);
608 irq_free_handler(0x02);
611 #endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */
614 * Absolute environment address for linker file.
616 GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);