3 * Denis Peter, d.peter@mpl.ch
4 * SPDX-License-Identifier: GPL-2.0+
6 /************************************************************************
7 * MACROS and register definitions for PATI Registers
8 ************************************************************************/
12 #define PLD_PART_ID 0x0
13 #define PLD_BOARD_TIMING 0x4
14 #define PLD_CONF_REG1 0x8
15 #define PLD_CONF_REG2 0xC
16 #define PLD_CONF_RES 0x10
18 #define SET_REG_BIT(y,x) (y<<(31-x))
19 #define GET_REG_BIT(y,x) ((y>>(31-x)) & 0x1L)
21 /* SDRAM Controller PLD_PART_ID */
22 /* 9 10 11 12 13 14 19 31 */
24 #define SDRAM_PART2 10
25 #define SDRAM_PART1 11
26 #define SDRAM_PART0 12
32 #define SDRAM_PART(x) ( \
33 (GET_REG_BIT(x,SDRAM_PART3)<<3) |\
34 (GET_REG_BIT(x,SDRAM_PART2)<<2) |\
35 (GET_REG_BIT(x,SDRAM_PART1)<<1) |\
36 (GET_REG_BIT(x,SDRAM_PART0)))
38 #define SDRAM_ID(x) ( \
39 (GET_REG_BIT(x,SDRAM_ID3)<<3) |\
40 (GET_REG_BIT(x,SDRAM_ID2)<<2) |\
41 (GET_REG_BIT(x,SDRAM_ID1)<<1) |\
42 (GET_REG_BIT(x,SDRAM_ID0)))
44 /* System Controller */
45 /* 0 1 3 4 5 16 20 28 29 30 */
46 #define SYSCNTR_PART4 0
47 #define SYSCNTR_PART3 1
48 #define SYSCNTR_PART2 3
49 #define SYSCNTR_PART1 4
50 #define SYSCNTR_PART0 5
51 #define SYSCNTR_ID4 16
52 #define SYSCNTR_ID3 20
53 #define SYSCNTR_ID2 28
54 #define SYSCNTR_ID1 29
55 #define SYSCNTR_ID0 30
57 #define SYSCNTR_PART(x) ( \
58 (GET_REG_BIT(x,SYSCNTR_PART4)<<4) |\
59 (GET_REG_BIT(x,SYSCNTR_PART3)<<3) |\
60 (GET_REG_BIT(x,SYSCNTR_PART2)<<2) |\
61 (GET_REG_BIT(x,SYSCNTR_PART1)<<1) |\
62 (GET_REG_BIT(x,SYSCNTR_PART0)))
64 #define SYSCNTR_ID(x) ( \
65 (GET_REG_BIT(x,SYSCNTR_ID4)<<4) |\
66 (GET_REG_BIT(x,SYSCNTR_ID3)<<3) |\
67 (GET_REG_BIT(x,SYSCNTR_ID2)<<2) |\
68 (GET_REG_BIT(x,SYSCNTR_ID1)<<1) |\
69 (GET_REG_BIT(x,SYSCNTR_ID0)))
71 /* SDRAM Controller PLD_BOARD_TIMING */
72 /* 9 10 11 12 13 14 19 31 */
81 /* System Controller */
82 /* 0 1 3 4 5 16 20 28 29 30 */
83 #define SYSCNTR_BREV0 0
84 #define SYSCNTR_BREV1 1
85 #define SYSCNTR_BREV2 3
86 #define SYSCNTR_BREV3 4
87 #define SYSCNTR_RES0 5
88 #define SYSCNTR_RES1 16
89 #define SYSCNTR_RES2 20
90 #define SYSCNTR_FLWAIT2 28
91 #define SYSCNTR_FLWAIT1 29
92 #define SYSCNTR_FLWAIT0 30
94 #define SYSCNTR_BREV(x) ( \
95 (GET_REG_BIT(x,SYSCNTR_BREV3)<<3) |\
96 (GET_REG_BIT(x,SYSCNTR_BREV2)<<2) |\
97 (GET_REG_BIT(x,SYSCNTR_BREV1)<<1) |\
98 (GET_REG_BIT(x,SYSCNTR_BREV0)))
100 #define GET_SYSCNTR_FLWAIT(x) ( \
101 (GET_REG_BIT(x,SYSCNTR_FLWAIT2)<<2) |\
102 (GET_REG_BIT(x,SYSCNTR_FLWAIT1)<<1) |\
103 (GET_REG_BIT(x,SYSCNTR_FLWAIT0)))
105 #define SET_SYSCNTR_FLWAIT(x) ( \
106 (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_FLWAIT2)) |\
107 (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_FLWAIT1)) |\
108 (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_FLWAIT0)))
110 /* SDRAM Controller REG 2*/
111 /* 9 10 11 12 13 14 19 31 */
113 #define SDRAM_MUX1 10
114 #define SDRAM_PDIS 11
115 #define SDRAM_RES1 12
116 #define SDRAM_RES2 13
117 #define SDRAM_RES3 14
118 #define SDRAM_RES4 19
121 #define GET_SDRAM_MUX(x) ( \
122 (GET_REG_BIT(x,SDRAM_MUX1)<<1)| \
123 (GET_REG_BIT(x,SDRAM_MUX0)))
126 /* System Controller */
127 /* 0 1 3 4 5 16 20 28 29 30 */
128 #define SYSCNTR_FLAG 0
130 #define SYSCNTR_BIND2 3
131 #define SYSCNTR_BIND1 4
132 #define SYSCNTR_BIND0 5
133 #define SYSCNTR_PRM 16
134 #define SYSCNTR_ICW 20
135 #define SYSCNTR_ISB2 28
136 #define SYSCNTR_ISB1 29
137 #define SYSCNTR_ISB0 30
139 #define GET_SYSCNTR_BOOTIND(x) ( \
140 (GET_REG_BIT(x,SYSCNTR_BIND2)<<2) |\
141 (GET_REG_BIT(x,SYSCNTR_BIND1)<<1) |\
142 (GET_REG_BIT(x,SYSCNTR_BIND0)))
144 #define SET_SYSCNTR_BOOTIND(x) ( \
145 (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_BIND2)) |\
146 (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_BIND1))| \
147 (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_BIND0)))
149 #define GET_SYSCNTR_ISB(x) ( \
150 (GET_REG_BIT(x,SYSCNTR_ISB2)<<2)| \
151 (GET_REG_BIT(x,SYSCNTR_ISB1)<<1)| \
152 (GET_REG_BIT(x,SYSCNTR_ISB0)))
154 #define SET_SYSCNTR_ISB(x) ( \
155 (SET_REG_BIT(((x & 0x04)!=0),SYSCNTR_ISB2))| \
156 (SET_REG_BIT(((x & 0x02)!=0)x,SYSCNTR_ISB))| \
157 (SET_REG_BIT(((x & 0x01)!=0)x,SYSCNTR_ISB0)))
159 /* SDRAM Controller REG 3*/
160 /* 9 10 11 12 13 14 19 31 */
162 #define SDRAM_CFG1 10
163 #define SDRAM_CFG2 11
164 #define SDRAM_CFG3 12
165 #define SDRAM_RES6 13
166 #define SDRAM_CFG5 14
167 #define SDRAM_CFG6 19
168 #define SDRAM_RES7 31
170 #define GET_SDRAM_CFG(x) ( \
171 (GET_REG_BIT(x,SDRAM_CFG6)<<4) |\
172 (GET_REG_BIT(x,SDRAM_CFG5)<<3) |\
173 (GET_REG_BIT(x,SDRAM_CFG3)<<2) |\
174 (GET_REG_BIT(x,SDRAM_CFG2)<<1) |\
175 (GET_REG_BIT(x,SDRAM_CFG1)))
177 /* System Controller */
178 /* 0 1 3 4 5 16 20 28 29 30 */
179 #define SYSCNTR_BDIS 0
180 #define SYSCNTR_PCIM 1
181 #define SYSCNTR_CFG0 3
182 #define SYSCNTR_CFG1 4
183 #define SYSCNTR_CFG2 5
184 #define SYSCNTR_CFG3 16
185 #define SYSCNTR_BOOTEN 20
186 #define SYSCNTR_CPU_VPP 28
187 #define SYSCNTR_FL_VPP 29
188 #define SYSCNTR_FL_WP 30
190 #define GET_SYSCNTR_CFG(x) ( \
191 (GET_REG_BIT(x,SYSCNTR_CFG3)<<3)| \
192 (GET_REG_BIT(x,SYSCNTR_CFG2)<<2)| \
193 (GET_REG_BIT(x,SYSCNTR_CFG1)<<1)| \
194 (GET_REG_BIT(x,SYSCNTR_CFG0)))
197 /***************************************************************
199 ***************************************************************/
201 #define PCI_VENDOR_ID_MPL 0x18E6
202 #define PCI_DEVICE_ID_PATI 0x00DA
204 #if defined(CONFIG_MIP405)
205 #define PATI_FIRMWARE_START_OFFSET 0x00300000
206 #define PATI_ISO_STRING "MEV-10084-001"
209 #define PATI_ENDIAN_MODE 0x3E
211 /*******************************************
216 * All addreses are mapped into the memory area
217 * (IO Area on some areas may also be possible)
218 * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
219 * - pci_space0_addr: configurable
220 * - pci_space1_addr configurable
224 * Local addresses (Remap)
225 * - SDRAM 0x06000000 Size 16MByte mask 0xff000000
226 * - EPLD CFG 0x07000000 Size 512Bytes
227 * - FLASH 0x03000000 Size up to 8MByte
228 * - CPU 0x01000000 Size 4MByte (only accessable if special configured)
232 * To prevent using large resources reservation on the host following
233 * PCI mapping is choosed:
234 * - pci_cfg_mem_base: fixed address to the PLX config area size 512Bytes
235 * - pci_space0_addr: configured to the EPLD Config Area size 256Bytes
236 * - pci_space1_addr: configured to the SDRAM Area size 1MBytes, this
237 * space is used to switch between SDRAM, Flash and CPU
241 /* Attribute definitions */
242 #define PATI_BUS_SIZE_8 0
243 #define PATI_BUS_SIZE_16 1
244 #define PATI_BUS_SIZE_32 3
246 #define PATI_SPACE0_MASK (0xFEFFFE00) /* Mask Attributes */
247 #define PATI_SPACE1_MASK (0x00000000) /* Mask Attributes */
249 #define PATI_EXTRA_LONG_EEPROM 1
251 #define SPACE0_TA_ENABLE (1<<6)
252 #define SPACE1_TA_ENABLE (1<<6)
255 #define PATI_LOC_CFG_ADDR 0x07000000 /* Local Address */
256 #define PATI_LOC_CFG_MASK 0xFFFFFF00 /* 256 Bytes */
258 #define PATI_LOC_CFG_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
259 #define PATI_LOC_CFG_BURST 0 /* No Burst */
260 #define PATI_LOC_CFG_NO_PREFETCH 1 /* No Prefetch */
261 #define PATI_LOC_CFG_TA_ENABLE 1 /* Enable TA */
263 #define PATI_LOC_CFG_SPACE0_ATTR ( \
264 PATI_LOC_CFG_BUS_SIZE | \
265 (PATI_LOC_CFG_TA_ENABLE << 6) | \
266 (PATI_LOC_CFG_NO_PREFETCH << 8) | \
267 (PATI_LOC_CFG_BURST << 24) | \
268 (PATI_EXTRA_LONG_EEPROM << 25))
270 /* should never be used */
271 #define PATI_LOC_CFG_SPACE1_ATTR ( \
272 PATI_LOC_CFG_BUS_SIZE | \
273 (PATI_LOC_CFG_TA_ENABLE << 6) | \
274 (PATI_LOC_CFG_NO_PREFETCH << 9) | \
275 (PATI_LOC_CFG_BURST << 8))
279 #define PATI_LOC_SDRAM_ADDR 0x06000000 /* Local Address */
280 #define PATI_LOC_SDRAM_MASK 0xFFF00000 /* 1MByte */
282 #define PATI_LOC_SDRAM_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
283 #define PATI_LOC_SDRAM_BURST 0 /* No Burst */
284 #define PATI_LOC_SDRAM_NO_PREFETCH 0 /* Prefetch */
285 #define PATI_LOC_SDRAM_TA_ENABLE 1 /* Enable TA */
287 /* should never be used */
288 #define PATI_LOC_SDRAM_SPACE0_ATTR ( \
289 PATI_LOC_SDRAM_BUS_SIZE | \
290 (PATI_LOC_SDRAM_TA_ENABLE << 6) | \
291 (PATI_LOC_SDRAM_NO_PREFETCH << 8) | \
292 (PATI_LOC_SDRAM_BURST << 24) | \
293 (PATI_EXTRA_LONG_EEPROM << 25))
295 #define PATI_LOC_SDRAM_SPACE1_ATTR ( \
296 PATI_LOC_SDRAM_BUS_SIZE | \
297 (PATI_LOC_SDRAM_TA_ENABLE << 6) | \
298 (PATI_LOC_SDRAM_NO_PREFETCH << 9) | \
299 (PATI_LOC_SDRAM_BURST << 8))
303 #define PATI_LOC_FLASH_ADDR 0x03000000 /* Local Address */
304 #define PATI_LOC_FLASH_MASK 0xFFF00000 /* 1MByte */
306 #define PATI_LOC_FLASH_BUS_SIZE PATI_BUS_SIZE_16 /* 16 Bit */
307 #define PATI_LOC_FLASH_BURST 0 /* No Burst */
308 #define PATI_LOC_FLASH_NO_PREFETCH 1 /* No Prefetch */
309 #define PATI_LOC_FLASH_TA_ENABLE 1 /* Enable TA */
311 /* should never be used */
312 #define PATI_LOC_FLASH_SPACE0_ATTR ( \
313 PATI_LOC_FLASH_BUS_SIZE | \
314 (PATI_LOC_FLASH_TA_ENABLE << 6) | \
315 (PATI_LOC_FLASH_NO_PREFETCH << 8) | \
316 (PATI_LOC_FLASH_BURST << 24) | \
317 (PATI_EXTRA_LONG_EEPROM << 25))
319 #define PATI_LOC_FLASH_SPACE1_ATTR ( \
320 PATI_LOC_FLASH_BUS_SIZE | \
321 (PATI_LOC_FLASH_TA_ENABLE << 6) | \
322 (PATI_LOC_FLASH_NO_PREFETCH << 9) | \
323 (PATI_LOC_FLASH_BURST << 8))
327 #define PATI_LOC_CPU_ADDR 0x01000000 /* Local Address */
328 #define PATI_LOC_CPU_MASK 0xFFF00000 /* 1Mbyte */
330 #define PATI_LOC_CPU_BUS_SIZE PATI_BUS_SIZE_32 /* 32 Bit */
331 #define PATI_LOC_CPU_BURST 0 /* No Burst */
332 #define PATI_LOC_CPU_NO_PREFETCH 1 /* No Prefetch */
333 #define PATI_LOC_CPU_TA_ENABLE 1 /* Enable TA */
335 /* should never be used */
336 #define PATI_LOC_CPU_SPACE0_ATTR ( \
337 PATI_LOC_CPU_BUS_SIZE | \
338 (PATI_LOC_CPU_TA_ENABLE << 6) | \
339 (PATI_LOC_CPU_NO_PREFETCH << 8) | \
340 (PATI_LOC_CPU_BURST << 24) | \
341 (PATI_EXTRA_CPU_EEPROM << 25))
343 #define PATI_LOC_CPU_SPACE1_ATTR ( \
344 PATI_LOC_CPU_BUS_SIZE | \
345 (PATI_LOC_CPU_TA_ENABLE << 6) | \
346 (PATI_LOC_CPU_NO_PREFETCH << 9) | \
347 (PATI_LOC_CPU_BURST << 8))
349 /***************************************************
350 * Hardware Config word definition
351 ***************************************************/
352 #define BOOT_EXT_FLASH 0x00000000
353 #define BOOT_INT_FLASH 0x00000004
354 #define BOOT_FROM_PCI 0x00000006
355 #define BOOT_FROM_SDRAM 0x00000005
357 #define ENABLE_INT_ARB 0x00000008
359 #define INITIAL_IRQ_PREF 0x00000010
361 #define INITIAL_MEM_0M 0x00000000
362 #define INITIAL_MEM_4M 0x00000080
363 #define INITIAL_MEM_8M 0x00000040
364 #define INITIAL_MEM_12M 0x000000C0
365 #define INITIAL_MEM_16M 0x00000020
366 #define INITIAL_MEM_20M 0x000000A0
367 #define INITIAL_MEM_24M 0x00000060
368 #define INITIAL_MEM_28M 0x000000E0
370 #define INTERNAL_HWCONF 0x00000100
372 #define LOCAL_CPU_SLAVE 0x00000200
374 #define DISABLE_MEM_CNTR 0x00000400
376 #define PCI_MASTER_ONLY 0x00000800
379 #define PATI_HW_START ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF))
380 #define PATI_HW_PCI_ONLY ((BOOT_EXT_FLASH | INITIAL_MEM_28M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
381 #define PATI_HW_CPU_ACC ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY))
382 #define PATI_HW_CPU_SLAVE ((BOOT_EXT_FLASH | INITIAL_MEM_12M | INITIAL_IRQ_PREF | PCI_MASTER_ONLY | LOCAL_CPU_SLAVE))
384 /***************************************************
385 * Direct Master Config
386 ***************************************************/
387 #define PATI_DMASTER_PCI_ADDR 0x01000000
388 #define PATI_BUS_MASTER 1
391 #define PATI_DMASTER_MASK 0xFFF00000 /* 1MByte */
392 #define PATI_DMASTER_ADDR 0x01000000 /* Local Address */
394 #define PATI_DMASTER_MEMORY_EN 0x00000001 /* 0x00000001 */
395 #define PATI_DMASTER_READ_AHEAD 0x00000004 /* 0x00000004 */
396 #define PATI_DMASTER_READ_NOT_AHEAD 0x00000000 /* 0x00000004 */
397 #define PATI_DMASTER_PRE_SIZE_CNTRL_0 0x00000000
398 #define PATI_DMASTER_PRE_SIZE_CNTRL_4 0x00000008
399 #define PATI_DMASTER_PRE_SIZE_CNTRL_8 0x00001000
400 #define PATI_DMASTER_PRE_SIZE_CNTRL_16 0x00001008
401 #define PATI_DMASTER_REL_PCI 0x00000000
402 #define PATI_DMASTER_NOT_REL_PCI 0x00000010
403 #define PATI_DMASTER_WR_INVAL 0x00000200
404 #define PATI_DMASTER_NOT_WR_INVAL 0x00000000
405 #define PATI_DMASTER_PRE_LIMIT 0x00000800
406 #define PATI_DMASTER_PRE_CONT 0x00000000
407 #define PATI_DMASTER_DELAY_WR_0 0x00000000
408 #define PATI_DMASTER_DELAY_WR_4 0x00004000
409 #define PATI_DMASTER_DELAY_WR_8 0x00008000
410 #define PATI_DMASTER_DELAY_WR_16 0x0000C000
412 #define PATI_DMASTER_PCI_ADDR_MASK 0xFFFF0000
414 #define PATI_DMASTER_ATTR \
415 PATI_DMASTER_MEMORY_EN | \
416 PATI_DMASTER_READ_AHEAD | \
417 PATI_DMASTER_PRE_SIZE_CNTRL_4 | \
418 PATI_DMASTER_REL_PCI | \
419 PATI_DMASTER_NOT_WR_INVAL | \
420 PATI_DMASTER_PRE_LIMIT | \
421 PATI_DMASTER_DELAY_WR_0
424 #endif /* #ifndef __PATI_H_ */