2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
7 * Modified for MPL VCMA9 by
8 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 * (C) Copyright 2002, 2003, 2004, 2005
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
35 /* register definitions */
37 #define PLD_BASE 0x28000000
38 #define MISC_REG 0x103
39 #define SDRAM_REG 0x106
40 #define BWSCON 0x48000000
41 #define CLKBASE 0x4C000000
45 #define GPIOBASE 0x56000000
49 /* some parameters for the board */
58 #define BURST_EN (0x1<<7)
61 #define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
62 #define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
63 #define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
64 #define B0_Tcoh_200 0x0 /* 0clk */
65 #define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */
66 #define B0_Tacp_200 0x0 /* page mode is not used */
67 #define B0_PMC_200 0x0 /* page mode disabled */
70 #define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
71 #define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
72 #define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
73 #define B0_Tcoh_250 0x0 /* 0clk */
74 #define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
75 #define B0_Tacp_250 0x0 /* page mode is not used */
76 #define B0_PMC_250 0x0 /* page mode disabled */
79 #define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
80 #define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
81 #define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
82 #define B0_Tcoh_266 0x0 /* 0clk */
83 #define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
84 #define B0_Tacp_266 0x0 /* page mode is not used */
85 #define B0_PMC_266 0x0 /* page mode disabled */
88 #define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */
89 #define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */
90 #define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */
91 #define B1_Tcoh_200 0x0 /* 0clk */
92 #define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */
93 #define B1_Tacp_200 0x0 /* page mode is not used */
94 #define B1_PMC_200 0x0 /* page mode disabled */
97 #define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */
98 #define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */
99 #define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */
100 #define B1_Tcoh_250 0x0 /* 0clk */
101 #define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */
102 #define B1_Tacp_250 0x0 /* page mode is not used */
103 #define B1_PMC_250 0x0 /* page mode disabled */
106 #define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */
107 #define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */
108 #define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */
109 #define B1_Tcoh_266 0x0 /* 0clk */
110 #define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */
111 #define B1_Tacp_266 0x0 /* page mode is not used */
112 #define B1_PMC_266 0x0 /* page mode disabled */
114 /* BANK2CON 200 + 250 + 266 */
115 #define B2_Tacs 0x3 /* 4clk */
116 #define B2_Tcos 0x3 /* 4clk */
117 #define B2_Tacc 0x7 /* 14clk */
118 #define B2_Tcoh 0x3 /* 4clk */
119 #define B2_Tcah 0x3 /* 4clk */
120 #define B2_Tacp 0x0 /* page mode is not used */
121 #define B2_PMC 0x0 /* page mode disabled */
123 /* BANK3CON 200 + 250 + 266 */
124 #define B3_Tacs 0x3 /* 4clk */
125 #define B3_Tcos 0x3 /* 4clk */
126 #define B3_Tacc 0x7 /* 14clk */
127 #define B3_Tcoh 0x3 /* 4clk */
128 #define B3_Tcah 0x3 /* 4clk */
129 #define B3_Tacp 0x0 /* page mode is not used */
130 #define B3_PMC 0x0 /* page mode disabled */
133 #define B4_Tacs_200 0x1 /* 1clk */
134 #define B4_Tcos_200 0x3 /* 4clk */
135 #define B4_Tacc_200 0x7 /* 14clk */
136 #define B4_Tcoh_200 0x3 /* 4clk */
137 #define B4_Tcah_200 0x2 /* 2clk */
138 #define B4_Tacp_200 0x0 /* page mode is not used */
139 #define B4_PMC_200 0x0 /* page mode disabled */
142 #define B4_Tacs_250 0x1 /* 1clk */
143 #define B4_Tcos_250 0x3 /* 4clk */
144 #define B4_Tacc_250 0x7 /* 14clk */
145 #define B4_Tcoh_250 0x3 /* 4clk */
146 #define B4_Tcah_250 0x2 /* 2clk */
147 #define B4_Tacp_250 0x0 /* page mode is not used */
148 #define B4_PMC_250 0x0 /* page mode disabled */
151 #define B4_Tacs_266 0x1 /* 1clk */
152 #define B4_Tcos_266 0x3 /* 4clk */
153 #define B4_Tacc_266 0x7 /* 14clk */
154 #define B4_Tcoh_266 0x3 /* 4clk */
155 #define B4_Tcah_266 0x2 /* 2clk */
156 #define B4_Tacp_266 0x0 /* page mode is not used */
157 #define B4_PMC_266 0x0 /* page mode disabled */
160 #define B5_Tacs_200 0x0 /* 0clk */
161 #define B5_Tcos_200 0x3 /* 4clk */
162 #define B5_Tacc_200 0x4 /* 6clk */
163 #define B5_Tcoh_200 0x3 /* 4clk */
164 #define B5_Tcah_200 0x1 /* 1clk */
165 #define B5_Tacp_200 0x0 /* page mode is not used */
166 #define B5_PMC_200 0x0 /* page mode disabled */
169 #define B5_Tacs_250 0x0 /* 0clk */
170 #define B5_Tcos_250 0x3 /* 4clk */
171 #define B5_Tacc_250 0x5 /* 8clk */
172 #define B5_Tcoh_250 0x3 /* 4clk */
173 #define B5_Tcah_250 0x1 /* 1clk */
174 #define B5_Tacp_250 0x0 /* page mode is not used */
175 #define B5_PMC_250 0x0 /* page mode disabled */
178 #define B5_Tacs_266 0x0 /* 0clk */
179 #define B5_Tcos_266 0x3 /* 4clk */
180 #define B5_Tacc_266 0x5 /* 8clk */
181 #define B5_Tcoh_266 0x3 /* 4clk */
182 #define B5_Tcah_266 0x1 /* 1clk */
183 #define B5_Tacp_266 0x0 /* page mode is not used */
184 #define B5_PMC_266 0x0 /* page mode disabled */
186 #define B6_MT 0x3 /* SDRAM */
187 #define B6_Trcd_200 0x0 /* 2clk */
188 #define B6_Trcd_250 0x1 /* 3clk */
189 #define B6_Trcd_266 0x1 /* 3clk */
190 #define B6_SCAN 0x2 /* 10bit */
192 #define B7_MT 0x3 /* SDRAM */
193 #define B7_Trcd_200 0x0 /* 2clk */
194 #define B7_Trcd_250 0x1 /* 3clk */
195 #define B7_Trcd_266 0x1 /* 3clk */
196 #define B7_SCAN 0x2 /* 10bit */
198 /* REFRESH parameter */
199 #define REFEN 0x1 /* Refresh enable */
200 #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
201 #define Trp_200 0x0 /* 2clk */
202 #define Trp_250 0x1 /* 3clk */
203 #define Trp_266 0x1 /* 3clk */
204 #define Tsrc_200 0x1 /* 5clk */
205 #define Tsrc_250 0x2 /* 6clk */
206 #define Tsrc_266 0x3 /* 7clk */
208 /* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */
209 #define REFCNT_200 489
210 /* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */
211 #define REFCNT_250 99
212 /* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */
214 /**************************************/
217 .word CONFIG_SYS_TEXT_BASE
221 /* use r0 to relocate DATA read/write to flash rather than memory ! */
225 /* enable minimal access to PLD */
226 ldr r1, [r13] /* load default BWSCON */
227 orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */
228 str r1, [r13] /* set BWSCON */
229 ldr r1, =0x7FF0 /* select slowest timing */
230 str r1, [r13, #0x18] /* set BANKCON5 */
234 ldrb r1, [r1, #MISC_REG]
236 tst r1, #FASTCPU /* FASTCPU available ? */
237 addeq r2, r2, #SETUPENTRY_SIZE
239 /* memory control configuration */
240 /* r2 = pointer into timing table */
241 /* r13 = pointer to MEM controller regs (starting with BWSCON) */
242 add r3, r2, #CSDATA_OFFSET
243 add r4, r3, #CSDATAENTRY_SIZE
250 /* PLD access is now possible */
252 /* r13 = pointer to MEM controller regs */
254 mov r4, #SDRAMENTRY_SIZE
255 ldrb r1, [r1, #SDRAM_REG]
256 /* calculate start and end point */
265 /* setup MPLL registers */
268 add r3, r2, #4 /* r3 points to PLL values */
269 str r4, [r1, #LOCKTIME]
271 str r5, [r1, #UPLLCON] /* writing PLL register */
272 /* !! order seems to be important !! */
279 str r4, [r1, #MPLLCON] /* writing PLL register */
280 /* !! order seems to be important !! */
287 /* everything is fine now */
291 /* the literal pools origin */
293 #define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \
302 #define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \
311 #define MK_BANKCON_SDRAM(trcd, scan) \
316 #define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \
325 /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */
326 .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0)
327 /* PLL values for USB clock */
328 .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
330 /* timing for 250 MHz*/
332 .equiv CSDATA_OFFSET, (. - SETUPDATA)
333 .word MK_BWSCON(DW16, \
336 DW16 + WAIT + UBLB, \
341 .word MK_BANKCON(B0_Tacs_250, \
349 .word MK_BANKCON(B1_Tacs_250, \
357 .word MK_BANKCON(B2_Tacs, \
365 .word MK_BANKCON(B3_Tacs, \
373 .word MK_BANKCON(B4_Tacs_250, \
381 .word MK_BANKCON(B5_Tacs_250, \
389 .equiv CSDATAENTRY_SIZE, (. - 0b)
392 .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
393 .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
394 .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
395 .word 0x32 + BURST_EN
398 .equiv SDRAMENTRY_SIZE, (. - 0b)
401 .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
402 .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
403 .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
404 .word 0x32 + BURST_EN
409 .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
410 .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
411 .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
412 .word 0x32 + BURST_EN
417 .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN)
418 .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN)
419 .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250)
420 .word 0x32 + BURST_EN
424 .equiv SETUPENTRY_SIZE, (. - SETUPDATA)
427 /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */
428 .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0)
429 /* PLL values for USB clock */
430 .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0)
432 /* timing for 200 MHz and default*/
433 .word MK_BWSCON(DW16, \
436 DW16 + WAIT + UBLB, \
441 .word MK_BANKCON(B0_Tacs_200, \
449 .word MK_BANKCON(B1_Tacs_200, \
457 .word MK_BANKCON(B2_Tacs, \
465 .word MK_BANKCON(B3_Tacs, \
473 .word MK_BANKCON(B4_Tacs_200, \
481 .word MK_BANKCON(B5_Tacs_200, \
490 .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
491 .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
492 .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
493 .word 0x32 + BURST_EN
498 .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
499 .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
500 .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
501 .word 0x32 + BURST_EN
506 .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
507 .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
508 .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
509 .word 0x32 + BURST_EN
514 .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN)
515 .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN)
516 .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200)
517 .word 0x32 + BURST_EN
521 .equiv SETUPDATA_SIZE, (. - SETUPDATA)