3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 #include <stdio_dev.h>
34 #include "../common/common_util.h"
36 DECLARE_GLOBAL_DATA_PTR;
40 #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
44 #elif FCLK_SPEED==1 /* Fout = 202.8MHz */
62 static inline void delay(unsigned long loops)
64 __asm__ volatile ("1:\n"
66 "bne 1b":"=r" (loops):"0" (loops));
70 * Miscellaneous platform dependent initialisations
75 S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
76 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
78 /* to reduce PLL lock time, adjust the LOCKTIME register */
79 clk_power->LOCKTIME = 0xFFFFFF;
82 clk_power->MPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
84 /* some delay between MPLL and UPLL */
88 clk_power->UPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
90 /* some delay between MPLL and UPLL */
93 /* set up the I/O ports */
94 gpio->GPACON = 0x007FFFFF;
95 gpio->GPBCON = 0x002AAAAA;
96 gpio->GPBUP = 0x000002BF;
97 gpio->GPCCON = 0xAAAAAAAA;
98 gpio->GPCUP = 0x0000FFFF;
99 gpio->GPDCON = 0xAAAAAAAA;
100 gpio->GPDUP = 0x0000FFFF;
101 gpio->GPECON = 0xAAAAAAAA;
102 gpio->GPEUP = 0x000037F7;
103 gpio->GPFCON = 0x00000000;
104 gpio->GPFUP = 0x00000000;
105 gpio->GPGCON = 0xFFEAFF5A;
106 gpio->GPGUP = 0x0000F0DC;
107 gpio->GPHCON = 0x0028AAAA;
108 gpio->GPHUP = 0x00000656;
110 /* setup correct IRQ modes for NIC */
111 gpio->EXTINT2 = (gpio->EXTINT2 & ~(7<<8)) | (4<<8); /* rising edge mode */
113 /* select USB port 2 to be host or device (fix to host for now) */
114 gpio->MISCCR |= 0x08;
117 gd->baudrate = CONFIG_BAUDRATE;
118 gd->have_console = 1;
121 /* arch number of VCMA9-Board */
122 gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
124 /* adress of boot parameters */
125 gd->bd->bi_boot_params = 0x30000100;
134 * NAND flash initialization.
136 #if defined(CONFIG_CMD_NAND)
138 nand_probe(ulong physadr);
141 static inline void NF_Reset(void)
146 NF_Cmd(0xFF); /* reset command */
147 for(i = 0; i < 10; i++); /* tWB = 100ns. */
148 NF_WaitRB(); /* wait 200~500us; */
153 static inline void NF_Init(void)
155 #if 0 /* a little bit too optimistic */
165 NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0));
166 /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */
167 /* 1 1 1 1, 1 xxx, r xxx, r xxx */
168 /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */
176 S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
180 printf("NAND flash probing at 0x%.8lX\n", (ulong)nand);
182 printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20);
187 * Get some Board/PLD Info
190 static u8 Get_PLD_ID(void)
192 VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
197 static u8 Get_PLD_BOARD(void)
199 VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
204 static u8 Get_PLD_SDRAM(void)
206 VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
211 static u8 Get_PLD_Version(void)
213 return((Get_PLD_ID() >> 4) & 0x0F);
216 static u8 Get_PLD_Revision(void)
218 return(Get_PLD_ID() & 0x0F);
222 static int Get_Board_Config(void)
224 u8 config = Get_PLD_BOARD() & 0x03;
233 static uchar Get_Board_PCB(void)
235 return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A');
238 static u8 Get_SDRAM_ChipNr(void)
240 switch ((Get_PLD_SDRAM() >> 4) & 0x0F) {
248 static ulong Get_SDRAM_ChipSize(void)
250 switch (Get_PLD_SDRAM() & 0x0F) {
251 case 0: return 16 * (1024*1024);
252 case 1: return 32 * (1024*1024);
253 case 2: return 8 * (1024*1024);
254 case 3: return 8 * (1024*1024);
258 static const char * Get_SDRAM_ChipGeom(void)
260 switch (Get_PLD_SDRAM() & 0x0F) {
261 case 0: return "4Mx8x4";
262 case 1: return "8Mx8x4";
263 case 2: return "2Mx8x4";
264 case 3: return "4Mx8x2";
265 default: return "unknown";
269 static void Show_VCMA9_Info(char *board_name, char *serial)
271 printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n",
272 board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision());
273 printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom());
278 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
279 gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr();
284 /* ------------------------------------------------------------------------- */
287 * Check Board Identity:
294 backup_t *b = (backup_t *) s;
296 i = getenv_r("serial#", s, 32);
297 if ((i < 0) || strncmp (s, "VCMA9", 5)) {
298 get_backup_values (b);
299 if (strncmp (b->signature, "MPL\0", 4) != 0) {
300 puts ("### No HW ID - assuming VCMA9");
302 b->serial_name[5] = 0;
303 Show_VCMA9_Info(b->serial_name, &b->serial_name[6]);
307 Show_VCMA9_Info(s, &s[6]);
314 extern void mem_test_reloc(void);
316 int last_stage_init(void)
320 stdio_print_current_devices();
325 /***************************************************************************
326 * some helping routines
328 #if !CONFIG_USB_KEYBOARD
329 int overwrite_console(void)
331 /* return TRUE if console should be overwritten */
336 /************************************************************************
338 ************************************************************************/
339 void print_vcma9_info(void)
344 if ((i = getenv_r("serial#", s, 32)) < 0) {
345 puts ("### No HW ID - assuming VCMA9");
346 printf("i %d", i*24);
349 Show_VCMA9_Info(s, &s[6]);