3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
6 * (C) Copyright 2002, 2010
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/arch/s3c24x0_cpu.h>
35 #include "../common/common_util.h"
37 DECLARE_GLOBAL_DATA_PTR;
40 * Miscellaneous platform dependent initialisations
43 int board_early_init_f(void)
45 struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
47 /* set up the I/O ports */
48 writel(0x007FFFFF, &gpio->gpacon);
49 writel(0x002AAAAA, &gpio->gpbcon);
50 writel(0x000002BF, &gpio->gpbup);
51 writel(0xAAAAAAAA, &gpio->gpccon);
52 writel(0x0000FFFF, &gpio->gpcup);
53 writel(0xAAAAAAAA, &gpio->gpdcon);
54 writel(0x0000FFFF, &gpio->gpdup);
55 writel(0xAAAAAAAA, &gpio->gpecon);
56 writel(0x000037F7, &gpio->gpeup);
57 writel(0x00000000, &gpio->gpfcon);
58 writel(0x00000000, &gpio->gpfup);
59 writel(0xFFEAFF5A, &gpio->gpgcon);
60 writel(0x0000F0DC, &gpio->gpgup);
61 writel(0x0028AAAA, &gpio->gphcon);
62 writel(0x00000656, &gpio->gphup);
64 /* setup correct IRQ modes for NIC (rising edge mode) */
65 writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2);
67 /* select USB port 2 to be host or device (setup as host for now) */
68 writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);
75 /* adress of boot parameters */
76 gd->bd->bi_boot_params = 0x30000100;
85 * Get some Board/PLD Info
88 static u8 get_pld_reg(enum vcma9_pld_regs reg)
90 return readb(VCMA9_PLD_BASE + reg);
93 static u8 get_pld_version(void)
95 return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F;
98 static u8 get_pld_revision(void)
100 return get_pld_reg(VCMA9_PLD_ID) & 0x0F;
103 static uchar get_board_pcb(void)
105 return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A';
108 static u8 get_nr_chips(void)
110 switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) {
118 static ulong get_chip_size(void)
120 switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
121 case 0: return 16 * (1024*1024);
122 case 1: return 32 * (1024*1024);
123 case 2: return 8 * (1024*1024);
124 case 3: return 8 * (1024*1024);
129 static const char *get_chip_geom(void)
131 switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) {
132 case 0: return "4Mx8x4";
133 case 1: return "8Mx8x4";
134 case 2: return "2Mx8x4";
135 case 3: return "4Mx8x2";
136 default: return "unknown";
140 static void vcma9_show_info(char *board_name, char *serial)
142 printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n",
144 get_board_pcb(), get_pld_version(), get_pld_revision());
145 printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom());
150 /* dram_init must store complete ramsize in gd->ram_size */
151 gd->ram_size = get_chip_size() * get_nr_chips();
156 * Check Board Identity:
163 backup_t *b = (backup_t *) s;
165 i = getenv_f("serial#", s, 32);
166 if ((i < 0) || strncmp (s, "VCMA9", 5)) {
167 get_backup_values (b);
168 if (strncmp (b->signature, "MPL\0", 4) != 0) {
169 puts ("### No HW ID - assuming VCMA9");
171 b->serial_name[5] = 0;
172 vcma9_show_info(b->serial_name, &b->serial_name[6]);
176 vcma9_show_info(s, &s[6]);
182 int board_late_init(void)
185 * check if environment is healthy, otherwise restore values
192 void vcma9_print_info(void)
194 char *s = getenv("serial#");
197 puts ("### No HW ID - assuming VCMA9");
200 vcma9_show_info(s, &s[6]);
204 #ifdef CONFIG_CMD_NET
205 int board_eth_init(bd_t *bis)
209 rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
216 * Hardcoded flash setup:
217 * Flash 0 is a non-CFI AMD AM29F400BB flash.
219 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
221 info->portwidth = FLASH_CFI_16BIT;
222 info->chipwidth = FLASH_CFI_BY16;
223 info->interface = FLASH_CFI_X16;