3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 * Kenati Technologies, Inc.
8 * board/ms7722se/lowlevel_init.S
10 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/processor.h>
16 #include <asm/macro.h>
19 * Board specific low level init code, called _very_ early in the
20 * startup sequence. Relocation to SDRAM has not happened yet, no
21 * stack is available, bss section has not been initialised, etc.
23 * (Note: As no stack is available, no subroutines can be called...).
34 * Cache Control Register
35 * Instruction Cache Invalidate
40 * Address of MMU Control Register
41 * TI == TLB Invalidate bit
43 write32 MMUCR_A, MMUCR_D
45 /* Address of Power Control Register 0 */
46 write32 MSTPCR0_A, MSTPCR0_D
48 /* Address of Power Control Register 2 */
49 write32 MSTPCR2_A, MSTPCR2_D
51 write16 SBSCR_A, SBSCR_D
53 write16 PSCR_A, PSCR_D
55 /* 0xA4520004 (Watchdog Control / Status Register) */
56 ! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
58 /* 0xA4520000 (Watchdog Count Register) */
59 write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
61 /* 0xA4520004 (Watchdog Control / Status Register) */
62 write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
64 /* 0xA4150000 Frequency control register */
65 write32 FRQCR_A, FRQCR_D
67 write32 CCR_A, CCR_D_2
71 write16 PSELA_A, PSELA_D
73 write16 DRVCR_A, DRVCR_D
75 write16 PCCR_A, PCCR_D
77 write16 PECR_A, PECR_D
79 write16 PJCR_A, PJCR_D
81 write16 PXCR_A, PXCR_D
83 write32 CMNCR_A, CMNCR_D
85 write32 CS0BCR_A, CS0BCR_D
87 write32 CS2BCR_A, CS2BCR_D
89 write32 CS4BCR_A, CS4BCR_D
91 write32 CS5ABCR_A, CS5ABCR_D
93 write32 CS5BBCR_A, CS5BBCR_D
95 write32 CS6ABCR_A, CS6ABCR_D
97 write32 CS0WCR_A, CS0WCR_D
99 write32 CS2WCR_A, CS2WCR_D
101 write32 CS4WCR_A, CS4WCR_D
103 write32 CS5AWCR_A, CS5AWCR_D
105 write32 CS5BWCR_A, CS5BWCR_D
107 write32 CS6AWCR_A, CS6AWCR_D
109 ! SDRAM initialization
110 write32 SDCR_A, SDCR_D
112 write32 SDWCR_A, SDWCR_D
114 write32 SDPCR_A, SDPCR_D
116 write32 RTCOR_A, RTCOR_D
118 write32 RTCSR_A, RTCSR_D
120 write8 SDMR3_A, SDMR3_D
122 ! BL bit off (init = ON) (?!?)
124 stc sr, r0 ! BL bit off(init=ON)
136 MSTPCR0_A: .long MSTPCR0
137 MSTPCR2_A: .long MSTPCR2
140 RWTCSR_A: .long RWTCSR
141 RWTCNT_A: .long RWTCNT
144 CCR_D: .long 0x00000800
145 CCR_D_2: .long 0x00000103
146 MMUCR_D: .long 0x00000004
147 MSTPCR0_D: .long 0x00001001
148 MSTPCR2_D: .long 0xffffffff
149 FRQCR_D: .long 0x07022538
151 PSELA_A: .long 0xa405014E
152 PSELA_D: .word 0x0A10
155 DRVCR_A: .long 0xa405018A
156 DRVCR_D: .word 0x0554
159 PCCR_A: .long 0xa4050104
163 PECR_A: .long 0xa4050108
167 PJCR_A: .long 0xa4050110
171 PXCR_A: .long 0xa4050148
176 CMNCR_D: .long 0x00000013
177 CS0BCR_A: .long CS0BCR ! Flash bank 1
178 CS0BCR_D: .long 0x24920400
179 CS2BCR_A: .long CS2BCR ! SRAM
180 CS2BCR_D: .long 0x24920400
181 CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
182 CS4BCR_D: .long 0x24920400
183 CS5ABCR_A: .long CS5ABCR ! Ext slot
184 CS5ABCR_D: .long 0x24920400
185 CS5BBCR_A: .long CS5BBCR ! USB controller
186 CS5BBCR_D: .long 0x24920400
187 CS6ABCR_A: .long CS6ABCR ! Ethernet
188 CS6ABCR_D: .long 0x24920400
190 CS0WCR_A: .long CS0WCR
191 CS0WCR_D: .long 0x00000300
192 CS2WCR_A: .long CS2WCR
193 CS2WCR_D: .long 0x00000300
194 CS4WCR_A: .long CS4WCR
195 CS4WCR_D: .long 0x00000300
196 CS5AWCR_A: .long CS5AWCR
197 CS5AWCR_D: .long 0x00000300
198 CS5BWCR_A: .long CS5BWCR
199 CS5BWCR_D: .long 0x00000300
200 CS6AWCR_A: .long CS6AWCR
201 CS6AWCR_D: .long 0x00000300
203 SDCR_A: .long SBSC_SDCR
204 SDCR_D: .long 0x00020809
205 SDWCR_A: .long SBSC_SDWCR
206 SDWCR_D: .long 0x00164d0d
207 SDPCR_A: .long SBSC_SDPCR
208 SDPCR_D: .long 0x00000087
209 RTCOR_A: .long SBSC_RTCOR
210 RTCOR_D: .long 0xA55A0034
211 RTCSR_A: .long SBSC_RTCSR
212 RTCSR_D: .long 0xA55A0010
213 SDMR3_A: .long 0xFE500180
218 SBSCR_D: .word 0x0040
220 RWTCSR_D_1: .word 0xA507
221 RWTCSR_D_2: .word 0xA507
222 RWTCNT_D: .word 0x5A00
225 SR_MASK_D: .long 0xEFFFFF0F