3 * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
6 * Kenati Technologies, Inc.
8 * board/ms7722se/lowlevel_init.S
10 * SPDX-License-Identifier: GPL-2.0+
16 #include <asm/processor.h>
17 #include <asm/macro.h>
20 * Board specific low level init code, called _very_ early in the
21 * startup sequence. Relocation to SDRAM has not happened yet, no
22 * stack is available, bss section has not been initialised, etc.
24 * (Note: As no stack is available, no subroutines can be called...).
35 * Cache Control Register
36 * Instruction Cache Invalidate
41 * Address of MMU Control Register
42 * TI == TLB Invalidate bit
44 write32 MMUCR_A, MMUCR_D
46 /* Address of Power Control Register 0 */
47 write32 MSTPCR0_A, MSTPCR0_D
49 /* Address of Power Control Register 2 */
50 write32 MSTPCR2_A, MSTPCR2_D
52 write16 SBSCR_A, SBSCR_D
54 write16 PSCR_A, PSCR_D
56 /* 0xA4520004 (Watchdog Control / Status Register) */
57 ! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
59 /* 0xA4520000 (Watchdog Count Register) */
60 write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
62 /* 0xA4520004 (Watchdog Control / Status Register) */
63 write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
65 /* 0xA4150000 Frequency control register */
66 write32 FRQCR_A, FRQCR_D
68 write32 CCR_A, CCR_D_2
72 write16 PSELA_A, PSELA_D
74 write16 DRVCR_A, DRVCR_D
76 write16 PCCR_A, PCCR_D
78 write16 PECR_A, PECR_D
80 write16 PJCR_A, PJCR_D
82 write16 PXCR_A, PXCR_D
84 write32 CMNCR_A, CMNCR_D
86 write32 CS0BCR_A, CS0BCR_D
88 write32 CS2BCR_A, CS2BCR_D
90 write32 CS4BCR_A, CS4BCR_D
92 write32 CS5ABCR_A, CS5ABCR_D
94 write32 CS5BBCR_A, CS5BBCR_D
96 write32 CS6ABCR_A, CS6ABCR_D
98 write32 CS0WCR_A, CS0WCR_D
100 write32 CS2WCR_A, CS2WCR_D
102 write32 CS4WCR_A, CS4WCR_D
104 write32 CS5AWCR_A, CS5AWCR_D
106 write32 CS5BWCR_A, CS5BWCR_D
108 write32 CS6AWCR_A, CS6AWCR_D
110 ! SDRAM initialization
111 write32 SDCR_A, SDCR_D
113 write32 SDWCR_A, SDWCR_D
115 write32 SDPCR_A, SDPCR_D
117 write32 RTCOR_A, RTCOR_D
119 write32 RTCSR_A, RTCSR_D
121 write8 SDMR3_A, SDMR3_D
123 ! BL bit off (init = ON) (?!?)
125 stc sr, r0 ! BL bit off(init=ON)
137 MSTPCR0_A: .long MSTPCR0
138 MSTPCR2_A: .long MSTPCR2
141 RWTCSR_A: .long RWTCSR
142 RWTCNT_A: .long RWTCNT
145 CCR_D: .long 0x00000800
146 CCR_D_2: .long 0x00000103
147 MMUCR_D: .long 0x00000004
148 MSTPCR0_D: .long 0x00001001
149 MSTPCR2_D: .long 0xffffffff
150 FRQCR_D: .long 0x07022538
152 PSELA_A: .long 0xa405014E
153 PSELA_D: .word 0x0A10
156 DRVCR_A: .long 0xa405018A
157 DRVCR_D: .word 0x0554
160 PCCR_A: .long 0xa4050104
164 PECR_A: .long 0xa4050108
168 PJCR_A: .long 0xa4050110
172 PXCR_A: .long 0xa4050148
177 CMNCR_D: .long 0x00000013
178 CS0BCR_A: .long CS0BCR ! Flash bank 1
179 CS0BCR_D: .long 0x24920400
180 CS2BCR_A: .long CS2BCR ! SRAM
181 CS2BCR_D: .long 0x24920400
182 CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
183 CS4BCR_D: .long 0x24920400
184 CS5ABCR_A: .long CS5ABCR ! Ext slot
185 CS5ABCR_D: .long 0x24920400
186 CS5BBCR_A: .long CS5BBCR ! USB controller
187 CS5BBCR_D: .long 0x24920400
188 CS6ABCR_A: .long CS6ABCR ! Ethernet
189 CS6ABCR_D: .long 0x24920400
191 CS0WCR_A: .long CS0WCR
192 CS0WCR_D: .long 0x00000300
193 CS2WCR_A: .long CS2WCR
194 CS2WCR_D: .long 0x00000300
195 CS4WCR_A: .long CS4WCR
196 CS4WCR_D: .long 0x00000300
197 CS5AWCR_A: .long CS5AWCR
198 CS5AWCR_D: .long 0x00000300
199 CS5BWCR_A: .long CS5BWCR
200 CS5BWCR_D: .long 0x00000300
201 CS6AWCR_A: .long CS6AWCR
202 CS6AWCR_D: .long 0x00000300
204 SDCR_A: .long SBSC_SDCR
205 SDCR_D: .long 0x00020809
206 SDWCR_A: .long SBSC_SDWCR
207 SDWCR_D: .long 0x00164d0d
208 SDPCR_A: .long SBSC_SDPCR
209 SDPCR_D: .long 0x00000087
210 RTCOR_A: .long SBSC_RTCOR
211 RTCOR_D: .long 0xA55A0034
212 RTCSR_A: .long SBSC_RTCSR
213 RTCSR_D: .long 0xA55A0010
214 SDMR3_A: .long 0xFE500180
219 SBSCR_D: .word 0x0040
221 RWTCSR_D_1: .word 0xA507
222 RWTCSR_D_2: .word 0xA507
223 RWTCNT_D: .word 0x5A00
226 SR_MASK_D: .long 0xEFFFFF0F