2 * (C) Copyright 2000-2004
3 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * SPDX-License-Identifier: GPL-2.0+
10 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
11 * U-Boot port on NetTA4 board
17 #include <status_led.h>
21 #ifdef CONFIG_HW_WATCHDOG
25 int fec8xx_miiphy_read(char *devname, unsigned char addr,
26 unsigned char reg, unsigned short *value);
27 int fec8xx_miiphy_write(char *devname, unsigned char addr,
28 unsigned char reg, unsigned short value);
30 /****************************************************************/
32 /* some sane bit macros */
33 #define _BD(_b) (1U << (31-(_b)))
34 #define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
36 #define _BW(_b) (1U << (15-(_b)))
37 #define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
39 #define _BB(_b) (1U << (7-(_b)))
40 #define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
42 #define _B(_b) _BD(_b)
43 #define _BR(_l, _h) _BDR(_l, _h)
45 /****************************************************************/
48 * Check Board Identity:
55 printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION);
59 /****************************************************************/
61 #define _NOT_USED_ 0xFFFFFFFF
63 /****************************************************************/
65 #define CS_0000 0x00000000
66 #define CS_0001 0x10000000
67 #define CS_0010 0x20000000
68 #define CS_0011 0x30000000
69 #define CS_0100 0x40000000
70 #define CS_0101 0x50000000
71 #define CS_0110 0x60000000
72 #define CS_0111 0x70000000
73 #define CS_1000 0x80000000
74 #define CS_1001 0x90000000
75 #define CS_1010 0xA0000000
76 #define CS_1011 0xB0000000
77 #define CS_1100 0xC0000000
78 #define CS_1101 0xD0000000
79 #define CS_1110 0xE0000000
80 #define CS_1111 0xF0000000
82 #define BS_0000 0x00000000
83 #define BS_0001 0x01000000
84 #define BS_0010 0x02000000
85 #define BS_0011 0x03000000
86 #define BS_0100 0x04000000
87 #define BS_0101 0x05000000
88 #define BS_0110 0x06000000
89 #define BS_0111 0x07000000
90 #define BS_1000 0x08000000
91 #define BS_1001 0x09000000
92 #define BS_1010 0x0A000000
93 #define BS_1011 0x0B000000
94 #define BS_1100 0x0C000000
95 #define BS_1101 0x0D000000
96 #define BS_1110 0x0E000000
97 #define BS_1111 0x0F000000
99 #define GPL0_AAAA 0x00000000
100 #define GPL0_AAA0 0x00200000
101 #define GPL0_AAA1 0x00300000
102 #define GPL0_000A 0x00800000
103 #define GPL0_0000 0x00A00000
104 #define GPL0_0001 0x00B00000
105 #define GPL0_111A 0x00C00000
106 #define GPL0_1110 0x00E00000
107 #define GPL0_1111 0x00F00000
109 #define GPL1_0000 0x00000000
110 #define GPL1_0001 0x00040000
111 #define GPL1_1110 0x00080000
112 #define GPL1_1111 0x000C0000
114 #define GPL2_0000 0x00000000
115 #define GPL2_0001 0x00010000
116 #define GPL2_1110 0x00020000
117 #define GPL2_1111 0x00030000
119 #define GPL3_0000 0x00000000
120 #define GPL3_0001 0x00004000
121 #define GPL3_1110 0x00008000
122 #define GPL3_1111 0x0000C000
124 #define GPL4_0000 0x00000000
125 #define GPL4_0001 0x00001000
126 #define GPL4_1110 0x00002000
127 #define GPL4_1111 0x00003000
129 #define GPL5_0000 0x00000000
130 #define GPL5_0001 0x00000400
131 #define GPL5_1110 0x00000800
132 #define GPL5_1111 0x00000C00
133 #define LOOP 0x00000080
135 #define EXEN 0x00000040
137 #define AMX_COL 0x00000000
138 #define AMX_ROW 0x00000020
139 #define AMX_MAR 0x00000030
141 #define NA 0x00000008
143 #define UTA 0x00000004
145 #define TODT 0x00000002
147 #define LAST 0x00000001
149 #define A10_AAAA GPL0_AAAA
150 #define A10_AAA0 GPL0_AAA0
151 #define A10_AAA1 GPL0_AAA1
152 #define A10_000A GPL0_000A
153 #define A10_0000 GPL0_0000
154 #define A10_0001 GPL0_0001
155 #define A10_111A GPL0_111A
156 #define A10_1110 GPL0_1110
157 #define A10_1111 GPL0_1111
159 #define RAS_0000 GPL1_0000
160 #define RAS_0001 GPL1_0001
161 #define RAS_1110 GPL1_1110
162 #define RAS_1111 GPL1_1111
164 #define CAS_0000 GPL2_0000
165 #define CAS_0001 GPL2_0001
166 #define CAS_1110 GPL2_1110
167 #define CAS_1111 GPL2_1111
169 #define WE_0000 GPL3_0000
170 #define WE_0001 GPL3_0001
171 #define WE_1110 GPL3_1110
172 #define WE_1111 GPL3_1111
174 /* #define CAS_LATENCY 3 */
175 #define CAS_LATENCY 2
177 const uint sdram_table[0x40] = {
181 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
182 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
183 CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
184 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
185 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
186 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
187 _NOT_USED_, _NOT_USED_,
190 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
191 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
192 CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
193 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
194 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
195 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
196 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
197 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
198 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
199 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
202 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
203 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
204 CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
205 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
206 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
207 _NOT_USED_, _NOT_USED_, _NOT_USED_,
210 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
211 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
212 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
213 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
214 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
215 CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
216 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
217 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
218 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
219 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
220 _NOT_USED_, _NOT_USED_, _NOT_USED_,
225 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
226 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
227 CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
228 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
229 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
231 _NOT_USED_, _NOT_USED_,
234 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
235 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
236 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
237 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
238 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
239 CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
240 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
241 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
243 _NOT_USED_, _NOT_USED_, _NOT_USED_,
244 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
247 CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
248 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
249 CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
250 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
252 _NOT_USED_, _NOT_USED_,
256 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
257 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
258 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
259 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
260 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
261 CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
262 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
264 _NOT_USED_, _NOT_USED_, _NOT_USED_,
265 _NOT_USED_, _NOT_USED_, _NOT_USED_,
266 _NOT_USED_, _NOT_USED_,
271 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
272 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
273 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
274 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
275 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
276 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
277 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
278 _NOT_USED_, _NOT_USED_,
281 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
285 CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
286 CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
289 #if CONFIG_NETPHONE_VERSION == 2
290 static const uint nandcs_table[0x40] = {
292 CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
293 CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
294 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
295 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
296 CS_0000 | GPL4_0000 | GPL5_1111,
297 CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
298 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
299 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
302 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
303 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
304 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
305 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
308 CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
309 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
310 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
311 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
312 CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
313 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
314 CS_0000 | GPL4_1111 | GPL5_1111,
315 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
318 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
319 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
320 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
321 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
324 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
325 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
326 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
338 /* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
339 /* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
340 #define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
343 #define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
344 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
345 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
347 void check_ram(unsigned int addr, unsigned int size)
349 unsigned int i, j, v, vv;
350 volatile unsigned int *p;
353 p = (unsigned int *)addr;
354 pv = (unsigned int)p;
355 for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
358 p = (unsigned int *)addr;
359 for (i = 0; i < size / sizeof(unsigned int); i++) {
363 printf("%p: read %08x instead of %08x\n", p, vv, v);
369 for (j = 0; j < 5; j++) {
371 case 0: v = 0x00000000; break;
372 case 1: v = 0xffffffff; break;
373 case 2: v = 0x55555555; break;
374 case 3: v = 0xaaaaaaaa; break;
375 default:v = 0xdeadbeef; break;
377 p = (unsigned int *)addr;
378 for (i = 0; i < size / sizeof(unsigned int); i++) {
382 printf("%p: read %08x instead of %08x\n", p, vv, v);
391 phys_size_t initdram(int board_type)
393 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
394 volatile memctl8xx_t *memctl = &immap->im_memctl;
397 upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
400 * Preliminary prescaler for refresh
402 memctl->memc_mptpr = MPTPR_PTP_DIV8;
404 memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
407 * Map controller bank 3 to the SDRAM bank at preliminary address.
409 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
410 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
412 memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
416 /* perform SDRAM initialisation sequence */
417 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
420 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
423 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
426 memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
434 *(volatile u32 *)0 = d1;
435 d2 = *(volatile u32 *)0;
437 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
442 *(volatile u32 *)0 = d1;
443 d2 = *(volatile u32 *)0;
445 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
450 size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
453 printf("SIZE is zero: LOOP on 0\n");
455 *(volatile u32 *)0 = 0;
456 (void)*(volatile u32 *)0;
463 /* ------------------------------------------------------------------------- */
465 void reset_phys(void)
471 /* reset the damn phys */
474 for (phyno = 0; phyno < 32; ++phyno) {
475 fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
478 fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
480 fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
481 BMCR_RESET | BMCR_ANENABLE);
486 /* ------------------------------------------------------------------------- */
488 /* GP = general purpose, SP = special purpose (on chip peripheral) */
490 /* bits that can have a special purpose or can be configured as inputs/outputs */
491 #define PA_GP_INMASK 0
492 #define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
495 #define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15))
496 #define PA_SP_DIRVAL 0
498 #define PB_GP_INMASK _B(28)
499 #define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
500 #define PB_SP_MASK (_BR(22, 25))
502 #define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30))
503 #define PB_SP_DIRVAL 0
505 #if CONFIG_NETPHONE_VERSION == 1
506 #define PC_GP_INMASK _BW(12)
507 #define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15))
508 #elif CONFIG_NETPHONE_VERSION == 2
509 #define PC_GP_INMASK (_BW(13) | _BW(15))
510 #define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12))
515 #define PC_GP_OUTVAL (_BW(10) | _BW(11))
516 #define PC_SP_DIRVAL 0
518 #if CONFIG_NETPHONE_VERSION == 1
519 #define PE_GP_INMASK _B(31)
520 #define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
521 #define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28))
522 #elif CONFIG_NETPHONE_VERSION == 2
523 #define PE_GP_INMASK _BR(28, 31)
524 #define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
525 #define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27))
529 #define PE_SP_DIRVAL 0
531 int board_early_init_f(void)
533 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
534 volatile iop8xx_t *ioport = &immap->im_ioport;
535 volatile cpm8xx_t *cpm = &immap->im_cpm;
536 volatile memctl8xx_t *memctl = &immap->im_memctl;
538 /* NAND chip select */
539 #if CONFIG_NETPHONE_VERSION == 1
540 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
541 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
542 #elif CONFIG_NETPHONE_VERSION == 2
543 upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
544 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
545 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
546 memctl->memc_mamr = 0; /* all clear */
549 /* DSP chip select */
550 memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
551 memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
553 #if CONFIG_NETPHONE_VERSION == 1
554 memctl->memc_br4 &= ~BR_V;
556 memctl->memc_br5 &= ~BR_V;
557 memctl->memc_br6 &= ~BR_V;
558 memctl->memc_br7 &= ~BR_V;
560 ioport->iop_padat = PA_GP_OUTVAL;
561 ioport->iop_paodr = PA_ODR_VAL;
562 ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
563 ioport->iop_papar = PA_SP_MASK;
565 cpm->cp_pbdat = PB_GP_OUTVAL;
566 cpm->cp_pbodr = PB_ODR_VAL;
567 cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
568 cpm->cp_pbpar = PB_SP_MASK;
570 ioport->iop_pcdat = PC_GP_OUTVAL;
571 ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
572 ioport->iop_pcso = PC_SOVAL;
573 ioport->iop_pcint = PC_INTVAL;
574 ioport->iop_pcpar = PC_SP_MASK;
576 cpm->cp_pedat = PE_GP_OUTVAL;
577 cpm->cp_peodr = PE_ODR_VAL;
578 cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
579 cpm->cp_pepar = PE_SP_MASK;
584 #ifdef CONFIG_HW_WATCHDOG
586 void hw_watchdog_reset(void)
588 /* XXX add here the really funky stuff */
593 #ifdef CONFIG_SHOW_ACTIVITY
595 static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */
597 /* called from timer interrupt every 1/CONFIG_SYS_HZ sec */
598 void board_show_activity(ulong timestamp)
600 if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
604 extern void phone_console_do_poll(void);
606 static void do_poll(void)
610 while (left_to_poll <= 0) {
611 phone_console_do_poll();
612 base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
615 } while (base != left_to_poll);
619 /* called when looping */
620 void show_activity(int arg)
627 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
628 int overwrite_console(void)
630 /* printf("overwrite_console called\n"); */
635 extern int drv_phone_init(void);
636 extern int drv_phone_use_me(void);
637 extern int drv_phone_is_idle(void);
639 int misc_init_r(void)
641 return drv_phone_init();
644 int last_stage_init(void)
648 #if CONFIG_NETPHONE_VERSION == 2
649 /* assert peripheral reset */
650 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
651 for (i = 0; i < 10; i++)
653 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |= _BW(12);
657 /* check in order to enable the local console */
658 left_to_poll = PHONE_CONSOLE_POLL_HZ;
659 i = CONFIG_SYS_HZ * 2;
669 if (drv_phone_use_me()) {
670 status_led_set(0, STATUS_LED_ON);
671 while (!drv_phone_is_idle()) {
673 udelay(1000000 / CONFIG_SYS_HZ);
676 console_assign(stdin, "phone");
677 console_assign(stdout, "phone");
678 console_assign(stderr, "phone");
679 setenv("bootdelay", "-1");
683 udelay(1000000 / CONFIG_SYS_HZ);
687 left_to_poll = PHONE_CONSOLE_POLL_HZ;