2 * (C) Copyright 2000-2004
3 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
27 * U-Boot port on NetTA4 board
36 #ifdef CONFIG_HW_WATCHDOG
40 /****************************************************************/
42 /* some sane bit macros */
43 #define _BD(_b) (1U << (31-(_b)))
44 #define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
46 #define _BW(_b) (1U << (15-(_b)))
47 #define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
49 #define _BB(_b) (1U << (7-(_b)))
50 #define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
52 #define _B(_b) _BD(_b)
53 #define _BR(_l, _h) _BDR(_l, _h)
55 /****************************************************************/
58 * Check Board Identity:
65 printf ("Intracom NetPhone V%d\n", CONFIG_NETPHONE_VERSION);
69 /****************************************************************/
71 #define _NOT_USED_ 0xFFFFFFFF
73 /****************************************************************/
75 #define CS_0000 0x00000000
76 #define CS_0001 0x10000000
77 #define CS_0010 0x20000000
78 #define CS_0011 0x30000000
79 #define CS_0100 0x40000000
80 #define CS_0101 0x50000000
81 #define CS_0110 0x60000000
82 #define CS_0111 0x70000000
83 #define CS_1000 0x80000000
84 #define CS_1001 0x90000000
85 #define CS_1010 0xA0000000
86 #define CS_1011 0xB0000000
87 #define CS_1100 0xC0000000
88 #define CS_1101 0xD0000000
89 #define CS_1110 0xE0000000
90 #define CS_1111 0xF0000000
92 #define BS_0000 0x00000000
93 #define BS_0001 0x01000000
94 #define BS_0010 0x02000000
95 #define BS_0011 0x03000000
96 #define BS_0100 0x04000000
97 #define BS_0101 0x05000000
98 #define BS_0110 0x06000000
99 #define BS_0111 0x07000000
100 #define BS_1000 0x08000000
101 #define BS_1001 0x09000000
102 #define BS_1010 0x0A000000
103 #define BS_1011 0x0B000000
104 #define BS_1100 0x0C000000
105 #define BS_1101 0x0D000000
106 #define BS_1110 0x0E000000
107 #define BS_1111 0x0F000000
109 #define GPL0_AAAA 0x00000000
110 #define GPL0_AAA0 0x00200000
111 #define GPL0_AAA1 0x00300000
112 #define GPL0_000A 0x00800000
113 #define GPL0_0000 0x00A00000
114 #define GPL0_0001 0x00B00000
115 #define GPL0_111A 0x00C00000
116 #define GPL0_1110 0x00E00000
117 #define GPL0_1111 0x00F00000
119 #define GPL1_0000 0x00000000
120 #define GPL1_0001 0x00040000
121 #define GPL1_1110 0x00080000
122 #define GPL1_1111 0x000C0000
124 #define GPL2_0000 0x00000000
125 #define GPL2_0001 0x00010000
126 #define GPL2_1110 0x00020000
127 #define GPL2_1111 0x00030000
129 #define GPL3_0000 0x00000000
130 #define GPL3_0001 0x00004000
131 #define GPL3_1110 0x00008000
132 #define GPL3_1111 0x0000C000
134 #define GPL4_0000 0x00000000
135 #define GPL4_0001 0x00001000
136 #define GPL4_1110 0x00002000
137 #define GPL4_1111 0x00003000
139 #define GPL5_0000 0x00000000
140 #define GPL5_0001 0x00000400
141 #define GPL5_1110 0x00000800
142 #define GPL5_1111 0x00000C00
143 #define LOOP 0x00000080
145 #define EXEN 0x00000040
147 #define AMX_COL 0x00000000
148 #define AMX_ROW 0x00000020
149 #define AMX_MAR 0x00000030
151 #define NA 0x00000008
153 #define UTA 0x00000004
155 #define TODT 0x00000002
157 #define LAST 0x00000001
159 #define A10_AAAA GPL0_AAAA
160 #define A10_AAA0 GPL0_AAA0
161 #define A10_AAA1 GPL0_AAA1
162 #define A10_000A GPL0_000A
163 #define A10_0000 GPL0_0000
164 #define A10_0001 GPL0_0001
165 #define A10_111A GPL0_111A
166 #define A10_1110 GPL0_1110
167 #define A10_1111 GPL0_1111
169 #define RAS_0000 GPL1_0000
170 #define RAS_0001 GPL1_0001
171 #define RAS_1110 GPL1_1110
172 #define RAS_1111 GPL1_1111
174 #define CAS_0000 GPL2_0000
175 #define CAS_0001 GPL2_0001
176 #define CAS_1110 GPL2_1110
177 #define CAS_1111 GPL2_1111
179 #define WE_0000 GPL3_0000
180 #define WE_0001 GPL3_0001
181 #define WE_1110 GPL3_1110
182 #define WE_1111 GPL3_1111
184 /* #define CAS_LATENCY 3 */
185 #define CAS_LATENCY 2
187 const uint sdram_table[0x40] = {
191 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
192 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
193 CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
194 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
195 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
196 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
197 _NOT_USED_, _NOT_USED_,
200 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
201 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
202 CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
203 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
204 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
205 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
206 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
207 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
208 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
209 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
212 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
213 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
214 CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
215 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
216 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
217 _NOT_USED_, _NOT_USED_, _NOT_USED_,
220 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
221 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
222 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
223 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
224 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
225 CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
226 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
227 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
228 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
229 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
230 _NOT_USED_, _NOT_USED_, _NOT_USED_,
235 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
236 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
237 CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
238 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
239 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
241 _NOT_USED_, _NOT_USED_,
244 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
245 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
246 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
247 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
248 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
249 CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
250 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
251 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
253 _NOT_USED_, _NOT_USED_, _NOT_USED_,
254 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
257 CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
258 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
259 CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
260 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
262 _NOT_USED_, _NOT_USED_,
266 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
267 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
268 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
269 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
270 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
271 CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
272 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
274 _NOT_USED_, _NOT_USED_, _NOT_USED_,
275 _NOT_USED_, _NOT_USED_, _NOT_USED_,
276 _NOT_USED_, _NOT_USED_,
281 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
282 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
283 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
284 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
285 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
286 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
287 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
288 _NOT_USED_, _NOT_USED_,
291 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
295 CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
296 CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
299 #if CONFIG_NETPHONE_VERSION == 2
300 static const uint nandcs_table[0x40] = {
302 CS_1000 | GPL4_1111 | GPL5_1111 | UTA,
303 CS_0000 | GPL4_1110 | GPL5_1111 | UTA,
304 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
305 CS_0000 | GPL4_0000 | GPL5_1111 | UTA,
306 CS_0000 | GPL4_0000 | GPL5_1111,
307 CS_0000 | GPL4_0001 | GPL5_1111 | UTA,
308 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
309 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST, /* NOP */
312 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
313 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
314 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
315 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
318 CS_1000 | GPL4_1111 | GPL5_1110 | UTA,
319 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
320 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
321 CS_0000 | GPL4_1111 | GPL5_0000 | UTA,
322 CS_0000 | GPL4_1111 | GPL5_0001 | UTA,
323 CS_0000 | GPL4_1111 | GPL5_1111 | UTA,
324 CS_0000 | GPL4_1111 | GPL5_1111,
325 CS_0011 | GPL4_1111 | GPL5_1111 | UTA | LAST,
328 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
329 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
330 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
331 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
334 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
335 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
336 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
348 /* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
349 /* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
350 #define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
353 #define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
354 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
355 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
357 void check_ram(unsigned int addr, unsigned int size)
359 unsigned int i, j, v, vv;
360 volatile unsigned int *p;
363 p = (unsigned int *)addr;
364 pv = (unsigned int)p;
365 for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
368 p = (unsigned int *)addr;
369 for (i = 0; i < size / sizeof(unsigned int); i++) {
373 printf("%p: read %08x instead of %08x\n", p, vv, v);
379 for (j = 0; j < 5; j++) {
381 case 0: v = 0x00000000; break;
382 case 1: v = 0xffffffff; break;
383 case 2: v = 0x55555555; break;
384 case 3: v = 0xaaaaaaaa; break;
385 default:v = 0xdeadbeef; break;
387 p = (unsigned int *)addr;
388 for (i = 0; i < size / sizeof(unsigned int); i++) {
392 printf("%p: read %08x instead of %08x\n", p, vv, v);
401 long int initdram(int board_type)
403 volatile immap_t *immap = (immap_t *) CFG_IMMR;
404 volatile memctl8xx_t *memctl = &immap->im_memctl;
407 upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(sdram_table[0]));
410 * Preliminary prescaler for refresh
412 memctl->memc_mptpr = MPTPR_PTP_DIV8;
414 memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
417 * Map controller bank 3 to the SDRAM bank at preliminary address.
419 memctl->memc_or3 = CFG_OR3_PRELIM;
420 memctl->memc_br3 = CFG_BR3_PRELIM;
422 memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
426 /* perform SDRAM initialisation sequence */
427 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
430 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
433 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
436 memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
444 *(volatile u32 *)0 = d1;
445 d2 = *(volatile u32 *)0;
447 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
452 *(volatile u32 *)0 = d1;
453 d2 = *(volatile u32 *)0;
455 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
460 size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
463 printf("SIZE is zero: LOOP on 0\n");
465 *(volatile u32 *)0 = 0;
466 (void)*(volatile u32 *)0;
473 /* ------------------------------------------------------------------------- */
475 void reset_phys(void)
481 /* reset the damn phys */
484 for (phyno = 0; phyno < 32; ++phyno) {
485 miiphy_read(phyno, PHY_PHYIDR1, &v);
488 miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
490 miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
495 /* ------------------------------------------------------------------------- */
497 /* GP = general purpose, SP = special purpose (on chip peripheral) */
499 /* bits that can have a special purpose or can be configured as inputs/outputs */
500 #define PA_GP_INMASK 0
501 #define PA_GP_OUTMASK (_BW(3) | _BW(7) | _BW(10) | _BW(14) | _BW(15))
504 #define PA_GP_OUTVAL (_BW(3) | _BW(14) | _BW(15))
505 #define PA_SP_DIRVAL 0
507 #define PB_GP_INMASK _B(28)
508 #define PB_GP_OUTMASK (_B(19) | _B(23) | _B(26) | _B(27) | _B(29) | _B(30))
509 #define PB_SP_MASK (_BR(22, 25))
511 #define PB_GP_OUTVAL (_B(26) | _B(27) | _B(29) | _B(30))
512 #define PB_SP_DIRVAL 0
514 #if CONFIG_NETPHONE_VERSION == 1
515 #define PC_GP_INMASK _BW(12)
516 #define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(13) | _BW(15))
517 #elif CONFIG_NETPHONE_VERSION == 2
518 #define PC_GP_INMASK (_BW(13) | _BW(15))
519 #define PC_GP_OUTMASK (_BW(10) | _BW(11) | _BW(12))
524 #define PC_GP_OUTVAL (_BW(10) | _BW(11))
525 #define PC_SP_DIRVAL 0
527 #if CONFIG_NETPHONE_VERSION == 1
528 #define PE_GP_INMASK _B(31)
529 #define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27) | _B(28) | _B(29) | _B(30))
530 #define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27) | _B(28))
531 #elif CONFIG_NETPHONE_VERSION == 2
532 #define PE_GP_INMASK _BR(28, 31)
533 #define PE_GP_OUTMASK (_B(17) | _B(18) |_B(20) | _B(24) | _B(27))
534 #define PE_GP_OUTVAL (_B(20) | _B(24) | _B(27))
538 #define PE_SP_DIRVAL 0
540 int board_early_init_f(void)
542 volatile immap_t *immap = (immap_t *) CFG_IMMR;
543 volatile iop8xx_t *ioport = &immap->im_ioport;
544 volatile cpm8xx_t *cpm = &immap->im_cpm;
545 volatile memctl8xx_t *memctl = &immap->im_memctl;
547 /* NAND chip select */
548 #if CONFIG_NETPHONE_VERSION == 1
549 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK | OR_EHTR | OR_TRLX);
550 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
551 #elif CONFIG_NETPHONE_VERSION == 2
552 upmconfig(UPMA, (uint *) nandcs_table, sizeof(nandcs_table) / sizeof(nandcs_table[0]));
553 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_G5LS);
554 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V | BR_MS_UPMA);
555 memctl->memc_mamr = 0; /* all clear */
558 /* DSP chip select */
559 memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_ACS_DIV2 | OR_SETA | OR_TRLX);
560 memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
562 #if CONFIG_NETPHONE_VERSION == 1
563 memctl->memc_br4 &= ~BR_V;
565 memctl->memc_br5 &= ~BR_V;
566 memctl->memc_br6 &= ~BR_V;
567 memctl->memc_br7 &= ~BR_V;
569 ioport->iop_padat = PA_GP_OUTVAL;
570 ioport->iop_paodr = PA_ODR_VAL;
571 ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
572 ioport->iop_papar = PA_SP_MASK;
574 cpm->cp_pbdat = PB_GP_OUTVAL;
575 cpm->cp_pbodr = PB_ODR_VAL;
576 cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
577 cpm->cp_pbpar = PB_SP_MASK;
579 ioport->iop_pcdat = PC_GP_OUTVAL;
580 ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
581 ioport->iop_pcso = PC_SOVAL;
582 ioport->iop_pcint = PC_INTVAL;
583 ioport->iop_pcpar = PC_SP_MASK;
585 cpm->cp_pedat = PE_GP_OUTVAL;
586 cpm->cp_peodr = PE_ODR_VAL;
587 cpm->cp_pedir = PE_GP_OUTMASK | PE_SP_DIRVAL;
588 cpm->cp_pepar = PE_SP_MASK;
593 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
595 #include <linux/mtd/nand.h>
597 extern ulong nand_probe(ulong physadr);
598 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
602 unsigned long totlen;
604 totlen = nand_probe(CFG_NAND_BASE);
605 printf ("%4lu MB\n", totlen >> 20);
609 #ifdef CONFIG_HW_WATCHDOG
611 void hw_watchdog_reset(void)
613 /* XXX add here the really funky stuff */
618 #ifdef CONFIG_SHOW_ACTIVITY
620 static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ; /* poll */
622 /* called from timer interrupt every 1/CFG_HZ sec */
623 void board_show_activity(ulong timestamp)
625 if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
629 extern void phone_console_do_poll(void);
631 static void do_poll(void)
635 while (left_to_poll <= 0) {
636 phone_console_do_poll();
637 base = left_to_poll + PHONE_CONSOLE_POLL_HZ;
640 } while (base != left_to_poll);
644 /* called when looping */
645 void show_activity(int arg)
652 #if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
653 int overwrite_console(void)
655 /* printf("overwrite_console called\n"); */
660 extern int drv_phone_init(void);
661 extern int drv_phone_use_me(void);
663 int misc_init_r(void)
665 return drv_phone_init();
668 int last_stage_init(void)
672 #if CONFIG_NETPHONE_VERSION == 2
673 /* assert peripheral reset */
674 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
675 for (i = 0; i < 10; i++)
677 ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |= _BW(12);
681 /* check in order to enable the local console */
682 left_to_poll = PHONE_CONSOLE_POLL_HZ;
693 if (drv_phone_use_me()) {
694 console_assign(stdin, "phone");
695 console_assign(stdout, "phone");
696 console_assign(stderr, "phone");
697 setenv("bootdelay", "-1");
701 udelay(1000000 / CFG_HZ);
705 left_to_poll = PHONE_CONSOLE_POLL_HZ;