2 *(C) Copyright 2005-2007 Netstal Maschinen AG
3 * Niklaus Giger (Niklaus.Giger@netstal.com)
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
23 #include <asm/processor.h>
25 #include <asm-ppc/u-boot.h>
26 #include "../common/nm_bsp.c"
28 DECLARE_GLOBAL_DATA_PTR;
30 #define HCU_MACH_VERSIONS_REGISTER (0x7C000000 + 0xF00000)
32 #define mtsdram(reg, data) { mtdcr(memcfga,reg);mtdcr(memcfgd,data); }
33 #define mfsdram(value, reg) { mtdcr(memcfga,reg); value = mfdcr(memcfgd); }
35 #define SDRAM_LEN 32*1024*1024 /* 32 MB -RAM */
37 #define DO_UGLY_SDRAM_WORKAROUND
40 /* HW_GENERATION_HCU wird nicht mehr unterstuetzt */
41 HW_GENERATION_HCU2 = 0x10,
42 HW_GENERATION_HCU3 = 0x10,
43 HW_GENERATION_HCU4 = 0x20,
44 HW_GENERATION_MCU = 0x08,
45 HW_GENERATION_MCU20 = 0x0a,
46 HW_GENERATION_MCU25 = 0x09,
49 void sysLedSet(u32 value);
50 long int spd_sdram(int(read_spd)(uint addr));
52 #ifdef CONFIG_SPD_EEPROM
57 void show_sdram_registers(void);
61 * This function is run very early, out of flash, and before devices are
62 * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
63 * of being in the init_sequence array.
65 * The SDRAM has been initialized already -- start.S:start called
66 * init.S:init_sdram early on -- but it is not yet being used for
67 * anything, not even stack. So be careful.
70 #define CPC0_CR0 0xb1 /* Chip control register 0 */
71 #define CPC0_CR1 0xb2 /* Chip control register 1 */
72 /* Attention: If you want 1 microsecs times from the external oscillator
73 * use 0x00804051. But this causes problems with u-boot and linux!
75 #define CPC0_CR1_VALUE 0x00004051
76 #define CPC0_ECR 0xaa /* Edge condition register */
77 #define EBC0_CFG 0x23 /* External Peripheral Control Register */
78 #define CPC0_EIRR 0xb6 /* External Interrupt Register */
81 int board_early_init_f (void)
83 /*-------------------------------------------------------------------+
84 | Interrupt controller setup for the HCU4 board.
85 | Note: IRQ 0-15 405GP internally generated; high; level sensitive
86 | IRQ 16 405GP internally generated; low; level sensitive
87 | IRQ 17-24 RESERVED/UNUSED
88 | IRQ 31 (EXT IRQ 6) (unused)
89 +-------------------------------------------------------------------*/
90 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
91 mtdcr (uicer, 0x00000000); /* disable all ints */
92 mtdcr (uiccr, 0x00000000); /* set all to be non-critical */
93 mtdcr (uicpr, 0xFFFFFF87); /* set int polarities */
94 mtdcr (uictr, 0x10000000); /* set int trigger levels */
95 mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
97 mtdcr(CPC0_CR1, CPC0_CR1_VALUE);
98 mtdcr(CPC0_ECR, 0x60606000);
99 mtdcr(CPC0_EIRR, 0x7c000000);
104 #ifdef CONFIG_BOARD_PRE_INIT
105 int board_pre_init (void)
107 return board_early_init_f ();
111 int checkboard (void)
114 u16 *boardVersReg = (u16 *) HCU_MACH_VERSIONS_REGISTER;
115 u16 generation = *boardVersReg & 0xf0;
116 u16 index = *boardVersReg & 0x0f;
118 /* Force /RTS to active. The board it not wired quite
119 correctly to use cts/rtc flow control, so just force the
120 /RST active and forget about it. */
121 writeb (readb (0xef600404) | 0x03, 0xef600404);
122 printf ("\nNetstal Maschinen AG ");
123 if (generation == HW_GENERATION_HCU3)
124 printf ("HCU3: index %d\n\n", index);
125 else if (generation == HW_GENERATION_HCU4)
126 printf ("HCU4: index %d\n\n", index);
127 /* GPIO here noch nicht richtig initialisert !!! */
129 for (j = 0; j < 7; j++) {
139 return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff;
142 void sysLedSet(u32 value /* value to place in LEDs */)
147 tmp = (tmp << 23) | 0x7FFFFF;
148 ledReg = (u32 *)GPIO0_OR;
153 * sdram_init - Dummy implementation for start.S, spd_sdram or initdram
156 void sdram_init(void)
162 void show_sdram_registers(void)
166 printf ("SDRAM Controller Registers --\n");
167 mfsdram(value, mem_mcopt1);
168 printf (" SDRAM0_CFG : 0x%08x\n", value);
169 mfsdram(value, mem_status);
170 printf (" SDRAM0_STATUS: 0x%08x\n", value);
171 mfsdram(value, mem_mb0cf);
172 printf (" SDRAM0_B0CR : 0x%08x\n", value);
173 mfsdram(value, mem_mb1cf);
174 printf (" SDRAM0_B1CR : 0x%08x\n", value);
175 mfsdram(value, mem_sdtr1);
176 printf (" SDRAM0_TR : 0x%08x\n", value);
177 mfsdram(value, mem_rtr);
178 printf (" SDRAM0_RTR : 0x%08x\n", value);
183 * this is even after checkboard. It returns the size of the SDRAM
184 * that we have installed. This function is called by board_init_f
185 * in lib_ppc/board.c to initialize the memory and return what I
186 * found. These are default value, which will be overridden later.
189 long int fixed_hcu4_sdram (int board_type)
192 printf (__FUNCTION__);
194 /* disable memory controller */
195 mtdcr (memcfga, mem_mcopt1);
196 mtdcr (memcfgd, 0x00000000);
200 /* Clear SDRAM0_BESR0 (Bus Error Syndrome Register) */
201 mtdcr (memcfga, mem_besra);
202 mtdcr (memcfgd, 0xffffffff);
204 /* Clear SDRAM0_BESR1 (Bus Error Syndrome Register) */
205 mtdcr (memcfga, mem_besrb);
206 mtdcr (memcfgd, 0xffffffff);
208 /* Clear SDRAM0_ECCCFG (disable ECC) */
209 mtdcr (memcfga, mem_ecccf);
210 mtdcr (memcfgd, 0x00000000);
212 /* Clear SDRAM0_ECCESR (ECC Error Syndrome Register) */
213 mtdcr (memcfga, mem_eccerr);
214 mtdcr (memcfgd, 0xffffffff);
216 /* Timing register: CASL=2, PTA=2, CTP=2, LDF=1, RFTA=5, RCD=2
219 mtdcr (memcfga, mem_sdtr1);
220 mtdcr (memcfgd, 0x008a4015);
222 /* Memory Bank 0 Config == BA=0x00000000, SZ=64M, AM=3, BE=1
225 mtdcr (memcfga, mem_mb0cf);
226 mtdcr (memcfgd, 0x00062001);
228 /* refresh timer = 0x400 */
229 mtdcr (memcfga, mem_rtr);
230 mtdcr (memcfgd, 0x04000000);
232 /* Power management idle timer set to the default. */
233 mtdcr (memcfga, mem_pmit);
234 mtdcr (memcfgd, 0x07c00000);
238 /* Enable banks (DCE=1, BPRF=1, ECCDD=1, EMDUL=1) TODO */
239 mtdcr (memcfga, mem_mcopt1);
240 mtdcr (memcfgd, 0x90800000);
243 printf ("%s: done\n", __FUNCTION__);
248 /*---------------------------------------------------------------------------+
250 *---------------------------------------------------------------------------*/
251 static u32 getSerialNr(void)
253 u32 *serial = (u32 *)CFG_FLASH_BASE;
255 if (*serial == 0xffffffff)
262 /*---------------------------------------------------------------------------+
264 *---------------------------------------------------------------------------*/
266 int misc_init_r(void)
268 char *s = getenv("ethaddr");
271 u32 serial = getSerialNr();
273 for (i = 0; i < 6; ++i) {
274 gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
276 s = (*e) ? e + 1 : e;
279 if (gd->bd->bi_enetaddr[3] == 0 &&
280 gd->bd->bi_enetaddr[4] == 0 &&
281 gd->bd->bi_enetaddr[5] == 0) {
283 /* [0..3] Must be in sync with CONFIG_ETHADDR */
284 gd->bd->bi_enetaddr[0] = 0x00;
285 gd->bd->bi_enetaddr[1] = 0x60;
286 gd->bd->bi_enetaddr[2] = 0x13;
287 gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
288 gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
289 gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xff;
290 sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
291 gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
292 gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
293 gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
294 printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
296 setenv ("ethaddr", ethaddr);
301 #ifdef DO_UGLY_SDRAM_WORKAROUND
304 void set_spd_default_value(unsigned int spd_addr,uchar def_val)
307 int res = i2c_read(SPD_EEPROM_ADDRESS, spd_addr, 1, &value, 1) ;
309 if (res == 0 && value == 0xff) {
310 res = i2c_write(SPD_EEPROM_ADDRESS,
311 spd_addr, 1, &def_val, 1) ;
313 printf("%s: Setting spd offset %3d to %3d res %d\n",
314 __FUNCTION__, spd_addr, def_val, res);
320 long int initdram(int board_type)
324 #if !defined(CONFIG_SPD_EEPROM)
325 dram_size = fixed_hcu4_sdram();
327 #ifdef DO_UGLY_SDRAM_WORKAROUND
328 /* Workaround if you have no working I2C-EEPROM-SPD-configuration */
329 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
330 set_spd_default_value(2, 4); /* SDRAM Type */
331 set_spd_default_value(7, 0); /* module width, high byte */
332 set_spd_default_value(12, 1); /* Refresh or 0x81 */
334 /* Only correct for HCU3 with 32 MB RAM*/
335 /* Number of bytes used by module manufacturer */
336 set_spd_default_value( 0, 128);
337 set_spd_default_value( 1, 11 ); /* Total SPD memory size */
338 set_spd_default_value( 2, 4 ); /* Memory type */
339 set_spd_default_value( 3, 12 ); /* Number of row address bits */
340 set_spd_default_value( 4, 9 ); /* Number of column address bits */
341 set_spd_default_value( 5, 1 ); /* Number of module rows */
342 set_spd_default_value( 6, 32 ); /* Module data width, LSB */
343 set_spd_default_value( 7, 0 ); /* Module data width, MSB */
344 set_spd_default_value( 8, 1 ); /* Module interface signal levels */
345 /* SDRAM cycle time for highest CL (Tclk) */
346 set_spd_default_value( 9, 112);
347 /* SDRAM access time from clock for highest CL (Tac) */
348 set_spd_default_value(10, 84 );
349 set_spd_default_value(11, 2 ); /* Module configuration type */
350 set_spd_default_value(12, 128); /* Refresh rate/type */
351 set_spd_default_value(13, 16 ); /* Primary SDRAM width */
352 set_spd_default_value(14, 8 ); /* Error Checking SDRAM width */
353 /* SDRAM device attributes, min clock delay for back to back */
354 /*random column addresses (Tccd) */
355 set_spd_default_value(15, 1 );
356 /* SDRAM device attributes, burst lengths supported */
357 set_spd_default_value(16, 143);
358 /* SDRAM device attributes, number of banks on SDRAM device */
359 set_spd_default_value(17, 4 );
360 /* SDRAM device attributes, CAS latency */
361 set_spd_default_value(18, 6 );
362 /* SDRAM device attributes, CS latency */
363 set_spd_default_value(19, 1 );
364 /* SDRAM device attributes, WE latency */
365 set_spd_default_value(20, 1 );
366 set_spd_default_value(21, 0 ); /* SDRAM module attributes */
367 /* SDRAM device attributes, general */
368 set_spd_default_value(22, 14 );
369 /* SDRAM cycle time for 2nd highest CL (Tclk) */
370 set_spd_default_value(23, 117);
371 /* SDRAM access time from clock for2nd highest CL (Tac) */
372 set_spd_default_value(24, 84 );
373 /* SDRAM cycle time for 3rd highest CL (Tclk) */
374 set_spd_default_value(25, 0 );
375 /* SDRAM access time from clock for3rd highest CL (Tac) */
376 set_spd_default_value(26, 0 );
377 set_spd_default_value(27, 15 ); /* Minimum row precharge time (Trp) */
378 /* Minimum row active to row active delay (Trrd) */
379 set_spd_default_value(28, 14 );
380 set_spd_default_value(29, 15 ); /* Minimum CAS to RAS delay (Trcd) */
381 set_spd_default_value(30, 37 ); /* Minimum RAS pulse width (Tras) */
382 set_spd_default_value(31, 8 ); /* Module bank density */
383 /* Command and Address signal input setup time */
384 set_spd_default_value(32, 21 );
385 /* Command and Address signal input hold time */
386 set_spd_default_value(33, 8 );
387 set_spd_default_value(34, 21 ); /* Data signal input setup time */
388 set_spd_default_value(35, 8 ); /* Data signal input hold time */
389 #endif /* DO_UGLY_SDRAM_WORKAROUND */
390 dram_size = spd_sdram(0);
394 show_sdram_registers();
397 #if defined(CFG_DRAM_TEST)
398 bcu4_testdram(dram_size);
399 printf("%s %d MB of SDRAM\n", __FUNCTION__, dram_size/(1024*1024));