2 *(C) Copyright 2005-2007 Netstal Maschinen AG
3 * Niklaus Giger (Niklaus.Giger@netstal.com)
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
22 #include <asm/processor.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 void sysLedSet(u32 value);
30 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
32 #define mtcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \
33 mtdcr(CPR0_CFGDATA,data); } while (0)
34 #define mfcpr0(reg, data) do { mtdcr(CPR0_CFGADDR,reg); \
35 data = mfdcr(CPR0_CFGDATA); } while (0)
37 #define SDR0_CP440 0x0180
40 * This function is run very early, out of flash, and before devices are
41 * initialized. It is called by lib_ppc/board.c:board_init_f by virtue
42 * of being in the init_sequence array.
44 * The SDRAM has been initialized already -- start.S:start called
45 * init.S:init_sdram early on -- but it is not yet being used for
46 * anything, not even stack. So be careful.
49 int board_early_init_f(void)
53 #undef BOOTSTRAP_OPTION_A_ACTIVE
54 #ifdef BOOTSTRAP_OPTION_A_ACTIVE
55 /* Booting with Bootstrap Option A
56 * First boot, with CPR0_ICFG_RLI_MASK == 0
57 * no we setup varios boot strapping register,
58 * then we do reset the PPC440 using a chip reset
59 * Unfortunately, we cannot use this option, as Nto1 is not set
60 * with Bootstrap Option A and cannot be changed later on by SW
61 * There are no other possible boostrap options with a 8 bit ROM
62 * See Errata (Version 1.04) CHIP_9
67 mfcpr0(CPR0_ICFG, cpr0icfg);
68 if ( ! (cpr0icfg & CPR0_ICFG_RLI_MASK ) ) {
69 mtcpr0(CPR0_MALD, 0x02000000);
70 mtcpr0(CPR0_OPBD, 0x02000000);
71 mtcpr0(CPR0_PERD, 0x05000000); /* 1:5 */
72 mtcpr0(CPR0_PLLC, 0x40000238);
73 mtcpr0(CPR0_PLLD, 0x01010414);
74 mtcpr0(CPR0_PRIMAD, 0x01000000);
75 mtcpr0(CPR0_PRIMBD, 0x01000000);
76 mtcpr0(CPR0_SPCID, 0x03000000);
77 mtsdr(SDR0_PFC0, 0x00003E00); /* [CTE] = 0 */
78 mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
79 mtcpr0(CPR0_ICFG, cpr0icfg | CPR0_ICFG_RLI_MASK);
82 * Initiate system reset in debug control register DBCR
85 #define SYSTEM_RESET 0x30000000
86 #define CHIP_RESET 0x20000000
87 mtspr(dbcr0, dbcr | CHIP_RESET );
89 mtsdr(SDR0_CP440, 0x0EAAEA02); /* [Nto1] = 1*/
91 mtdcr(ebccfga, xbcfg);
92 mtdcr(ebccfgd, 0xb8400000);
94 /*--------------------------------------------------------------------
96 *-------------------------------------------------------------------*/
97 /* test-only: take GPIO init from pcs440ep ???? in config file */
98 out32(GPIO0_OR, 0x00000000);
99 out32(GPIO0_TCR, 0x7C2FF1CF);
100 out32(GPIO0_OSRL, 0x40055000);
101 out32(GPIO0_OSRH, 0x00000000);
102 out32(GPIO0_TSRL, 0x40055000);
103 out32(GPIO0_TSRH, 0x00000400);
104 out32(GPIO0_ISR1L, 0x40000000);
105 out32(GPIO0_ISR1H, 0x00000000);
106 out32(GPIO0_ISR2L, 0x00000000);
107 out32(GPIO0_ISR2H, 0x00000000);
108 out32(GPIO0_ISR3L, 0x00000000);
109 out32(GPIO0_ISR3H, 0x00000000);
111 out32(GPIO1_OR, 0x00000000);
112 out32(GPIO1_TCR, 0xC6007FFF);
113 out32(GPIO1_OSRL, 0x00140000);
114 out32(GPIO1_OSRH, 0x00000000);
115 out32(GPIO1_TSRL, 0x00000000);
116 out32(GPIO1_TSRH, 0x00000000);
117 out32(GPIO1_ISR1L, 0x05415555);
118 out32(GPIO1_ISR1H, 0x40000000);
119 out32(GPIO1_ISR2L, 0x00000000);
120 out32(GPIO1_ISR2H, 0x00000000);
121 out32(GPIO1_ISR3L, 0x00000000);
122 out32(GPIO1_ISR3H, 0x00000000);
124 /*--------------------------------------------------------------------
125 * Setup the interrupt controller polarities, triggers, etc.
126 *-------------------------------------------------------------------*/
127 mtdcr(uic0sr, 0xffffffff); /* clear all */
128 mtdcr(uic0er, 0x00000000); /* disable all */
129 mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
130 mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */
131 mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
132 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
133 mtdcr(uic0sr, 0xffffffff); /* clear all */
135 mtdcr(uic1sr, 0xffffffff); /* clear all */
136 mtdcr(uic1er, 0x00000000); /* disable all */
137 mtdcr(uic1cr, 0x00000000); /* all non-critical */
138 mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
139 mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
140 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
141 mtdcr(uic1sr, 0xffffffff); /* clear all */
143 mtdcr(uic2sr, 0xffffffff); /* clear all */
144 mtdcr(uic2er, 0x00000000); /* disable all */
145 mtdcr(uic2cr, 0x00000000); /* all non-critical */
146 mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
147 mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
148 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
149 mtdcr(uic2sr, 0xffffffff); /* clear all */
150 mtsdr(sdr_pfc0, 0x00003E00); /* Pin function: */
151 mtsdr(sdr_pfc1, 0x00848000); /* Pin function: UART0 has 4 pins */
153 /* PCI arbiter enabled */
154 mfsdr(sdr_pci0, reg);
155 mtsdr(sdr_pci0, 0x80000000 | reg);
159 /* setup BOOT FLASH */
160 mtsdr(SDR0_CUST0, 0xC0082350);
165 #ifdef CONFIG_BOARD_PRE_INIT
166 int board_pre_init (void)
168 return board_early_init_f ();
174 /* HW_GENERATION_HCU1 is no longer supported */
175 HW_GENERATION_HCU2 = 0x10,
176 HW_GENERATION_HCU3 = 0x10,
177 HW_GENERATION_HCU4 = 0x20,
178 HW_GENERATION_HCU5 = 0x30,
179 HW_GENERATION_MCU = 0x08,
180 HW_GENERATION_MCU20 = 0x0a,
181 HW_GENERATION_MCU25 = 0x09,
184 int checkboard (void)
186 #define SDR0_ECID0 0x0080
187 #define SDR0_ECID1 0x0081
188 #define SDR0_ECID2 0x0082
189 #define SDR0_ECID3 0x0083
191 uint16_t *hwVersReg = (uint16_t *) HCU_HW_VERSION_REGISTER;
192 uint16_t *boardVersReg = (uint16_t *) HCU_CPLD_VERSION_REGISTER;
193 uint16_t generation = *boardVersReg & 0xf0;
194 uint16_t index = *boardVersReg & 0x0f;
195 ulong ecid0, ecid1, ecid2, ecid3;
196 printf ("Netstal Maschinen AG: ");
197 if (generation == HW_GENERATION_HCU3)
198 printf ("HCU3: index %d", index);
199 else if (generation == HW_GENERATION_HCU4)
200 printf ("HCU4: index %d", index);
201 else if (generation == HW_GENERATION_HCU5)
202 printf ("HCU5: index %d", index);
203 printf (" HW 0x%02x\n", *hwVersReg & 0xff);
204 mfsdr(SDR0_ECID0, ecid0);
205 mfsdr(SDR0_ECID1, ecid1);
206 mfsdr(SDR0_ECID2, ecid2);
207 mfsdr(SDR0_ECID3, ecid3);
209 printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
210 for (j=0; j < 6;j++) {
217 #define SYS_IO_ADDRESS 0xcce00000
221 return in16(SYS_IO_ADDRESS) & 0x3f;
224 void sysLedSet(u32 value /* value to place in LEDs */)
226 out16(SYS_IO_ADDRESS, value);
229 /*---------------------------------------------------------------------------+
231 *---------------------------------------------------------------------------*/
232 static u32 getSerialNr(void)
234 u32 *serial = (u32 *)CFG_FLASH_BASE;
235 if (*serial == 0xffffffff) {
242 /*---------------------------------------------------------------------------+
244 *---------------------------------------------------------------------------*/
246 #define DEFAULT_ETH_ADDR "ethaddr"
247 /* ethaddr for first or etha1ddr for second ethernet */
249 int misc_init_r(void)
251 char *s = getenv(DEFAULT_ETH_ADDR);
254 u32 serial = getSerialNr();
255 unsigned long usb2d0cr = 0;
256 unsigned long usb2phy0cr, usb2h0cr = 0;
257 unsigned long sdr0_pfc1;
259 for (i = 0; i < 6; ++i) {
260 gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
262 s = (*e) ? e + 1 : e;
264 if (gd->bd->bi_enetaddr[3] == 0 &&
265 gd->bd->bi_enetaddr[4] == 0 &&
266 gd->bd->bi_enetaddr[5] == 0) {
268 /* Must be in sync with CONFIG_ETHADDR */
269 gd->bd->bi_enetaddr[0] = 0x00;
270 gd->bd->bi_enetaddr[1] = 0x60;
271 gd->bd->bi_enetaddr[2] = 0x13;
272 gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
273 gd->bd->bi_enetaddr[4] = (serial >> 8) & 0xff;
274 /* byte[5].bit 0 must be zero */
275 gd->bd->bi_enetaddr[5] = (serial >> 0) & 0xfe;
276 sprintf (ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
277 gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
278 gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
279 gd->bd->bi_enetaddr[4], gd->bd->bi_enetaddr[5]) ;
280 printf("%s: Setting eth %s serial 0x%x\n", __FUNCTION__,
282 setenv (DEFAULT_ETH_ADDR, ethaddr);
284 #ifdef CFG_ENV_IS_IN_FLASH
285 /* Monitor protection ON by default */
286 (void)flash_protect(FLAG_PROTECT_SET,
291 /* Env protection ON by default */
292 (void)flash_protect(FLAG_PROTECT_SET,
294 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
303 mfsdr(SDR0_PFC1, sdr0_pfc1);
304 mfsdr(SDR0_USB2D0CR, usb2d0cr);
305 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
306 mfsdr(SDR0_USB2H0CR, usb2h0cr);
308 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
309 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
310 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
311 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
312 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
313 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
314 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
315 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
316 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
317 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
319 /* An 8-bit/60MHz interface is the only possible alternative
320 when connecting the Device to the PHY */
321 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
322 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
324 /* To enable the USB 2.0 Device function through the UTMI interface */
325 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
326 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1*/
328 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
329 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
331 mtsdr(SDR0_PFC1, sdr0_pfc1);
332 mtsdr(SDR0_USB2D0CR, usb2d0cr);
333 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
334 mtsdr(SDR0_USB2H0CR, usb2h0cr);
338 mtsdr(SDR0_SRST1, 0x00000000);
340 mtsdr(SDR0_SRST0, 0x00000000);
342 printf("USB: Host(int phy) Device(ext phy)\n");
347 /*************************************************************************
350 * This routine is called just prior to registering the hose and gives
351 * the board the opportunity to check things. Returning a value of zero
352 * indicates that things are bad & PCI initialization should be aborted.
354 * Different boards may wish to customize the pci controller structure
355 * (add regions, override default access routines, etc) or perform
356 * certain pre-initialization actions.
358 ************************************************************************/
359 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
360 int pci_pre_init(struct pci_controller *hose)
364 /*-------------------------------------------------------------------+
365 * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM.
366 * Workaround: Disable write pipelining to DDR SDRAM by setting
368 *-------------------------------------------------------------------*/
370 /*-------------------------------------------------------------------+
371 | Set priority for all PLB3 devices to 0.
372 | Set PLB3 arbiter to fair mode.
373 +-------------------------------------------------------------------*/
374 mfsdr(sdr_amp1, addr);
375 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
376 addr = mfdcr(plb3_acr);
377 // mtdcr(plb3_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */
378 mtdcr(plb3_acr, addr | 0x80000000); /* Sequoia */
380 /*-------------------------------------------------------------------+
381 | Set priority for all PLB4 devices to 0.
382 +-------------------------------------------------------------------*/
383 mfsdr(sdr_amp0, addr);
384 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
385 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
386 // mtdcr(plb4_acr, addr & ~plb1_acr_wrp_mask); /* ngngng */
387 mtdcr(plb4_acr, addr); /* Sequoia */
389 /*-------------------------------------------------------------------+
390 | Set Nebula PLB4 arbiter to fair mode.
391 +-------------------------------------------------------------------*/
393 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
394 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
395 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
396 // addr = (addr & ~plb0_acr_wrp_mask) ; /* ngngng */
397 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; /* Sequoia */
399 // mtdcr(plb0_acr, addr); /* Sequoia */
400 mtdcr(plb0_acr, 0); // PATCH HAB: WRITE PIPELINING OFF
404 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
405 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
406 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
407 addr = (addr & ~plb1_acr_wrp_mask) ;
408 // mtdcr(plb1_acr, addr); /* Sequoia */
409 mtdcr(plb1_acr, 0); // PATCH HAB: WRITE PIPELINING OFF
413 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
415 /*************************************************************************
418 * The bootstrap configuration provides default settings for the pci
419 * inbound map (PIM). But the bootstrap config choices are limited and
420 * may not be sufficient for a given board.
422 ************************************************************************/
423 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
424 void pci_target_init(struct pci_controller *hose)
426 /*-------------------------------------------------------------+
427 * Set up Direct MMIO registers
428 *-------------------------------------------------------------*/
429 /*-------------------------------------------------------------+
430 | PowerPC440EPX PCI Master configuration.
431 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
432 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address
433 | 0xA0000000-0xDFFFFFFF
434 | Use byte reversed out routines to handle endianess.
435 | Make this region non-prefetchable.
436 +-------------------------------------------------------------*/
437 /* PMM0 Mask/Attribute - disabled b4 setting */
438 out32r(PCIX0_PMM0MA, 0x00000000);
439 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
440 /* PMM0 PCI Low Address */
441 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
442 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
443 /* 512M + No prefetching, and enable region */
444 out32r(PCIX0_PMM0MA, 0xE0000001);
446 /* PMM0 Mask/Attribute - disabled b4 setting */
447 out32r(PCIX0_PMM1MA, 0x00000000);
448 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
449 /* PMM0 PCI Low Address */
450 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
451 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
452 /* 512M + No prefetching, and enable region */
453 out32r(PCIX0_PMM1MA, 0xE0000001);
455 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
456 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
457 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
458 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
460 /*------------------------------------------------------------------+
461 * Set up Configuration registers
462 *------------------------------------------------------------------*/
464 /* Program the board's subsystem id/vendor id */
465 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
466 CFG_PCI_SUBSYS_VENDORID);
467 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
469 /* Configure command register as bus master */
470 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
472 /* 240nS PCI clock */
473 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
475 /* No error reporting */
476 pci_write_config_word(0, PCI_ERREN, 0);
478 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
481 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
483 /*************************************************************************
486 ************************************************************************/
487 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
488 void pci_master_init(struct pci_controller *hose)
490 unsigned short temp_short;
492 /*---------------------------------------------------------------+
493 | Write the PowerPC440 EP PCI Configuration regs.
494 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
495 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
496 +--------------------------------------------------------------*/
497 pci_read_config_word(0, PCI_COMMAND, &temp_short);
498 pci_write_config_word(0, PCI_COMMAND,
499 temp_short | PCI_COMMAND_MASTER |
503 /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
505 /*************************************************************************
508 * This routine is called to determine if a pci scan should be
509 * performed. With various hardware environments (especially cPCI and
510 * PPMC) it's insufficient to depend on the state of the arbiter enable
511 * bit in the strap register, or generic host/adapter assumptions.
513 * Rather than hard-code a bad assumption in the general 440 code, the
514 * 440 pci code requires the board to decide at runtime.
516 * Return 0 for adapter mode, non-zero for host (monarch) mode.
519 ************************************************************************/
520 #if defined(CONFIG_PCI)
521 int is_pci_host(struct pci_controller *hose)
525 #endif /* defined(CONFIG_PCI) */