3 * Niklaus Giger (Niklaus.Giger@netstal.com)
5 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
7 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
8 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
9 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
12 * Stefan Roese, DENX Software Engineering, sr@denx.de.
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 /* define DEBUG for debug output */
34 #include <asm/processor.h>
39 void sysLedSet(u32 value);
40 void dcbz_area(u32 start_address, u32 num_bytes);
43 #define DDR_DCR_BASE 0x10
44 #define ddrcfga (DDR_DCR_BASE+0x0) /* DDR configuration address reg */
45 #define ddrcfgd (DDR_DCR_BASE+0x1) /* DDR configuration data reg */
47 #define DDR0_01_INT_MASK_MASK 0x000000FF
48 #define DDR0_00_INT_ACK_ALL 0x7F000000
49 #define DDR0_01_INT_MASK_ALL_ON 0x000000FF
50 #define DDR0_01_INT_MASK_ALL_OFF 0x00000000
52 #define DDR0_17_DLLLOCKREG_MASK 0x00010000 /* Read only */
53 #define DDR0_17_DLLLOCKREG_UNLOCKED 0x00000000
54 #define DDR0_17_DLLLOCKREG_LOCKED 0x00010000
58 #define DDR0_22_CTRL_RAW_MASK 0x03000000
59 #define DDR0_22_CTRL_RAW_ECC_DISABLE 0x00000000 /* ECC not enabled */
60 #define DDR0_22_CTRL_RAW_ECC_CHECK_ONLY 0x01000000 /* ECC no correction */
61 #define DDR0_22_CTRL_RAW_NO_ECC_RAM 0x02000000 /* Not a ECC RAM*/
62 #define DDR0_22_CTRL_RAW_ECC_ENABLE 0x03000000 /* ECC correcting on */
63 #define DDR0_03_CASLAT_DECODE(n) ((((unsigned long)(n))>>16)&0x7)
65 #ifdef CFG_ENABLE_SDRAM_CACHE
66 #define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on DDR2 */
68 #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on DDR2 */
71 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
73 void board_add_ram_info(int use_default)
75 PPC440_SYS_INFO board_cfg;
77 mfsdram(DDR0_22, val);
78 val &= DDR0_22_CTRL_RAW_MASK;
80 case DDR0_22_CTRL_RAW_ECC_DISABLE:
81 puts(" (ECC disabled");
83 case DDR0_22_CTRL_RAW_ECC_CHECK_ONLY:
84 puts(" (ECC check only");
86 case DDR0_22_CTRL_RAW_NO_ECC_RAM:
89 case DDR0_22_CTRL_RAW_ECC_ENABLE:
90 puts(" (ECC enabled");
94 get_sys_info(&board_cfg);
95 printf(", %d MHz", (board_cfg.freqPLB * 2) / 1000000);
97 mfsdram(DDR0_03, val);
98 val = DDR0_03_CASLAT_DECODE(val);
99 printf(", CL%d)", val);
102 /*--------------------------------------------------------------------
104 *--------------------------------------------------------------------*/
105 static int wait_for_dlllock(void)
110 /* -----------------------------------------------------------+
111 * Wait for the DCC master delay line to finish calibration
112 * ----------------------------------------------------------*/
113 mtdcr(ddrcfga, DDR0_17);
114 val = DDR0_17_DLLLOCKREG_UNLOCKED;
116 while (wait != 0xffff) {
117 val = mfdcr(ddrcfgd);
118 if ((val & DDR0_17_DLLLOCKREG_MASK) ==
119 DDR0_17_DLLLOCKREG_LOCKED)
120 /* dlllockreg bit on */
125 debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
126 debug("Waiting for dlllockreg bit to raise\n");
131 /***********************************************************************
133 * sdram_panic -- Panic if we cannot configure the sdram correctly
135 ************************************************************************/
136 void sdram_panic(const char *reason)
138 printf("\n%s: reason %s", __FUNCTION__, reason);
145 #ifdef CONFIG_DDR_ECC
146 static void blank_string(int size)
150 for (i=0; i<size; i++)
152 for (i=0; i<size; i++)
154 for (i=0; i<size; i++)
157 /*---------------------------------------------------------------------------+
159 *---------------------------------------------------------------------------*/
160 static void program_ecc(unsigned long start_address, unsigned long num_bytes,
161 unsigned long tlb_word2_i_value)
163 unsigned long current_address= start_address;
167 char str[] = "ECC generation -";
168 char slash[] = "\\|/-\\|/-";
175 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
176 /* ECC bit set method for non-cached memory */
177 /* This takes various seconds */
178 for(current_address = 0; current_address < num_bytes;
179 current_address += sizeof(u32)) {
180 *(u32 *)current_address = 0;
181 if ((current_address % (2 << 20)) == 0) {
183 putc(slash[loopi++ % 8]);
187 /* ECC bit set method for cached memory */
188 /* Fast method, no noticeable delay */
189 dcbz_area(start_address, num_bytes);
192 blank_string(strlen(str));
194 /* Clear error status */
195 mfsdram(DDR0_00, val);
196 mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
198 /* Set 'int_mask' parameter to functionnal value */
199 mfsdram(DDR0_01, val);
200 mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
201 DDR0_01_INT_MASK_ALL_OFF));
208 /***********************************************************************
210 * initdram -- 440EPx's DDR controller is a DENALI Core
212 ************************************************************************/
213 long int initdram (int board_type)
215 #define HCU_HW_SDRAM_CONFIG_MASK 0x7
216 #define INVALID_HW_CONFIG "Invalid HW-Config"
217 u16 *hwVersReg = (u16 *) HCU_HW_VERSION_REGISTER;
218 unsigned int dram_size = 0;
220 mtsdram(DDR0_02, 0x00000000);
222 /* Values must be kept in sync with Excel-table <<A0001492.>> ! */
223 mtsdram(DDR0_00, 0x0000190A);
224 mtsdram(DDR0_01, 0x01000000);
225 mtsdram(DDR0_03, 0x02030602);
226 mtsdram(DDR0_04, 0x0A020200);
227 mtsdram(DDR0_05, 0x02020307);
228 switch (*hwVersReg & HCU_HW_SDRAM_CONFIG_MASK) {
230 dram_size = 128 * 1024 * 1024 ;
231 mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */
232 mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */
233 mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */
236 dram_size = 256 * 1024 * 1024 ;
237 mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */
238 mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */
239 mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */
242 sdram_panic(INVALID_HW_CONFIG);
245 dram_size -= 16 * 1024 * 1024;
246 mtsdram(DDR0_07, 0x00090100);
248 * TCPD=200 cycles of clock input is required to lock the DLL.
249 * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001);
251 mtsdram(DDR0_08, 0x02C80001);
252 mtsdram(DDR0_09, 0x00011D5F);
253 mtsdram(DDR0_10, 0x00000100);
254 mtsdram(DDR0_12, 0x00000003);
255 mtsdram(DDR0_14, 0x00000000);
256 mtsdram(DDR0_17, 0x1D000000);
257 mtsdram(DDR0_18, 0x1D1D1D1D);
258 mtsdram(DDR0_19, 0x1D1D1D1D);
259 mtsdram(DDR0_20, 0x0B0B0B0B);
260 mtsdram(DDR0_21, 0x0B0B0B0B);
261 #define ECC_RAM 0x03267F0B
262 #define NO_ECC_RAM 0x00267F0B
263 #ifdef CONFIG_DDR_ECC
264 mtsdram(DDR0_22, ECC_RAM);
266 mtsdram(DDR0_22, NO_ECC_RAM);
269 mtsdram(DDR0_23, 0x00000000);
270 mtsdram(DDR0_24, 0x01020001);
271 mtsdram(DDR0_26, 0x2D930517);
272 mtsdram(DDR0_27, 0x00008236);
273 mtsdram(DDR0_28, 0x00000000);
274 mtsdram(DDR0_31, 0x00000000);
275 mtsdram(DDR0_42, 0x01000006);
276 mtsdram(DDR0_44, 0x00000003);
277 mtsdram(DDR0_02, 0x00000001);
279 mtsdram(DDR0_00, 0x40000000); /* Zero init bit */
282 * Program tlb entries for this size (dynamic)
284 program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
287 * Setup 2nd TLB with same physical address but different virtual
288 * address with cache enabled. This is done for fast ECC generation.
290 program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
292 #ifdef CONFIG_DDR_ECC
294 * If ECC is enabled, initialize the parity bits.
296 program_ecc(CFG_DDR_CACHED_ADDR, dram_size, 0);