2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
26 * U-Boot port on NetTA4 board
34 #ifdef CONFIG_HW_WATCHDOG
38 /****************************************************************/
40 /* some sane bit macros */
41 #define _BD(_b) (1U << (31-(_b)))
42 #define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
44 #define _BW(_b) (1U << (15-(_b)))
45 #define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
47 #define _BB(_b) (1U << (7-(_b)))
48 #define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
50 #define _B(_b) _BD(_b)
51 #define _BR(_l, _h) _BDR(_l, _h)
53 /****************************************************************/
56 * Check Board Identity:
63 printf ("Intracom NETTA"
64 #if defined(CONFIG_NETTA_ISDN)
67 #if defined(CONFIG_NETTA_6412)
77 /****************************************************************/
79 #define _NOT_USED_ 0xFFFFFFFF
81 /****************************************************************/
83 #define CS_0000 0x00000000
84 #define CS_0001 0x10000000
85 #define CS_0010 0x20000000
86 #define CS_0011 0x30000000
87 #define CS_0100 0x40000000
88 #define CS_0101 0x50000000
89 #define CS_0110 0x60000000
90 #define CS_0111 0x70000000
91 #define CS_1000 0x80000000
92 #define CS_1001 0x90000000
93 #define CS_1010 0xA0000000
94 #define CS_1011 0xB0000000
95 #define CS_1100 0xC0000000
96 #define CS_1101 0xD0000000
97 #define CS_1110 0xE0000000
98 #define CS_1111 0xF0000000
100 #define BS_0000 0x00000000
101 #define BS_0001 0x01000000
102 #define BS_0010 0x02000000
103 #define BS_0011 0x03000000
104 #define BS_0100 0x04000000
105 #define BS_0101 0x05000000
106 #define BS_0110 0x06000000
107 #define BS_0111 0x07000000
108 #define BS_1000 0x08000000
109 #define BS_1001 0x09000000
110 #define BS_1010 0x0A000000
111 #define BS_1011 0x0B000000
112 #define BS_1100 0x0C000000
113 #define BS_1101 0x0D000000
114 #define BS_1110 0x0E000000
115 #define BS_1111 0x0F000000
117 #define A10_AAAA 0x00000000
118 #define A10_AAA0 0x00200000
119 #define A10_AAA1 0x00300000
120 #define A10_000A 0x00800000
121 #define A10_0000 0x00A00000
122 #define A10_0001 0x00B00000
123 #define A10_111A 0x00C00000
124 #define A10_1110 0x00E00000
125 #define A10_1111 0x00F00000
127 #define RAS_0000 0x00000000
128 #define RAS_0001 0x00040000
129 #define RAS_1110 0x00080000
130 #define RAS_1111 0x000C0000
132 #define CAS_0000 0x00000000
133 #define CAS_0001 0x00010000
134 #define CAS_1110 0x00020000
135 #define CAS_1111 0x00030000
137 #define WE_0000 0x00000000
138 #define WE_0001 0x00004000
139 #define WE_1110 0x00008000
140 #define WE_1111 0x0000C000
142 #define GPL4_0000 0x00000000
143 #define GPL4_0001 0x00001000
144 #define GPL4_1110 0x00002000
145 #define GPL4_1111 0x00003000
147 #define GPL5_0000 0x00000000
148 #define GPL5_0001 0x00000400
149 #define GPL5_1110 0x00000800
150 #define GPL5_1111 0x00000C00
151 #define LOOP 0x00000080
153 #define EXEN 0x00000040
155 #define AMX_COL 0x00000000
156 #define AMX_ROW 0x00000020
157 #define AMX_MAR 0x00000030
159 #define NA 0x00000008
161 #define UTA 0x00000004
163 #define TODT 0x00000002
165 #define LAST 0x00000001
167 /* #define CAS_LATENCY 3 */
168 #define CAS_LATENCY 2
170 const uint sdram_table[0x40] = {
174 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
175 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
176 CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
177 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
178 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
179 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
180 _NOT_USED_, _NOT_USED_,
183 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
184 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
185 CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
186 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
187 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
188 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
189 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
190 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
191 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
192 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
195 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
196 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
197 CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
198 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
199 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
200 _NOT_USED_, _NOT_USED_, _NOT_USED_,
203 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
204 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
205 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
206 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
207 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
208 CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
209 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
210 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
211 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
212 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
213 _NOT_USED_, _NOT_USED_, _NOT_USED_,
218 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
219 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
220 CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
221 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
222 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
224 _NOT_USED_, _NOT_USED_,
227 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
228 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
229 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
230 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
231 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
232 CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
233 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
234 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
236 _NOT_USED_, _NOT_USED_, _NOT_USED_,
237 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
240 CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
241 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
242 CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
243 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
245 _NOT_USED_, _NOT_USED_,
249 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
250 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
251 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
252 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
253 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
254 CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
255 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
257 _NOT_USED_, _NOT_USED_, _NOT_USED_,
258 _NOT_USED_, _NOT_USED_, _NOT_USED_,
259 _NOT_USED_, _NOT_USED_,
264 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
265 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
266 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
267 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
268 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
269 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
270 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
271 _NOT_USED_, _NOT_USED_,
274 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
278 CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
279 CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
282 /* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
283 /* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
284 #define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
287 #define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
288 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
289 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
291 void check_ram(unsigned int addr, unsigned int size)
293 unsigned int i, j, v, vv;
294 volatile unsigned int *p;
297 p = (unsigned int *)addr;
298 pv = (unsigned int)p;
299 for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
302 p = (unsigned int *)addr;
303 for (i = 0; i < size / sizeof(unsigned int); i++) {
307 printf("%p: read %08x instead of %08x\n", p, vv, v);
313 for (j = 0; j < 5; j++) {
315 case 0: v = 0x00000000; break;
316 case 1: v = 0xffffffff; break;
317 case 2: v = 0x55555555; break;
318 case 3: v = 0xaaaaaaaa; break;
319 default:v = 0xdeadbeef; break;
321 p = (unsigned int *)addr;
322 for (i = 0; i < size / sizeof(unsigned int); i++) {
326 printf("%p: read %08x instead of %08x\n", p, vv, v);
335 long int initdram(int board_type)
337 volatile immap_t *immap = (immap_t *) CFG_IMMR;
338 volatile memctl8xx_t *memctl = &immap->im_memctl;
341 upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
344 * Preliminary prescaler for refresh
346 memctl->memc_mptpr = MPTPR_PTP_DIV8;
348 memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
351 * Map controller bank 3 to the SDRAM bank at preliminary address.
353 memctl->memc_or3 = CFG_OR3_PRELIM;
354 memctl->memc_br3 = CFG_BR3_PRELIM;
356 memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE; /* no refresh yet */
360 /* perform SDRAM initialisation sequence */
361 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
364 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
367 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
370 memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
378 *(volatile u32 *)0 = d1;
379 d2 = *(volatile u32 *)0;
381 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
386 *(volatile u32 *)0 = d1;
387 d2 = *(volatile u32 *)0;
389 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
394 size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
398 check_ram(( 0 << 20), (2 << 20));
399 printf("check 16\n");
400 check_ram((16 << 20), (2 << 20));
401 printf("check 32\n");
402 check_ram((32 << 20), (2 << 20));
403 printf("check 48\n");
404 check_ram((48 << 20), (2 << 20));
408 printf("SIZE is zero: LOOP on 0\n");
410 *(volatile u32 *)0 = 0;
411 (void)*(volatile u32 *)0;
418 /* ------------------------------------------------------------------------- */
420 int misc_init_r(void)
425 void reset_phys(void)
430 /* reset the damn phys */
433 for (phyno = 0; phyno < 32; ++phyno) {
434 miiphy_read(phyno, PHY_PHYIDR1, &v);
437 miiphy_write(phyno, PHY_BMCR, PHY_BMCR_POWD);
439 miiphy_write(phyno, PHY_BMCR, PHY_BMCR_RESET | PHY_BMCR_AUTON);
444 extern int board_dsp_reset(void);
446 int last_stage_init(void)
451 r = board_dsp_reset();
453 printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
457 /* ------------------------------------------------------------------------- */
459 /* GP = general purpose, SP = special purpose (on chip peripheral) */
461 /* bits that can have a special purpose or can be configured as inputs/outputs */
462 #define PA_GP_INMASK (_BWR(3) | _BWR(7, 9) | _BW(11))
463 #define PA_GP_OUTMASK (_BW(6) | _BW(10) | _BWR(12, 15))
464 #define PA_SP_MASK (_BWR(0, 2) | _BWR(4, 5))
466 #define PA_GP_OUTVAL (_BW(13) | _BWR(14, 15))
467 #define PA_SP_DIRVAL 0
469 #define PB_GP_INMASK (_B(28) | _B(31))
470 #define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
471 #define PB_SP_MASK (_BR(22, 25))
473 #define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
474 #define PB_SP_DIRVAL 0
476 #define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
477 #define PC_GP_OUTMASK (_BW(6) | _BW(12))
478 #define PC_SP_MASK (_BW(4) | _BW(8))
480 #define PC_INTVAL _BW(7)
481 #define PC_GP_OUTVAL (_BW(6) | _BW(12))
482 #define PC_SP_DIRVAL 0
484 #define PD_GP_INMASK 0
485 #define PD_GP_OUTMASK _BWR(3, 15)
488 #if defined(CONFIG_NETTA_6412)
490 #define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
494 #define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11))
498 #define PD_SP_DIRVAL 0
500 int board_early_init_f(void)
502 volatile immap_t *immap = (immap_t *) CFG_IMMR;
503 volatile iop8xx_t *ioport = &immap->im_ioport;
504 volatile cpm8xx_t *cpm = &immap->im_cpm;
505 volatile memctl8xx_t *memctl = &immap->im_memctl;
507 /* CS1: NAND chip select */
508 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
509 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
510 #if !defined(CONFIG_NETTA_6412)
512 memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
513 memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
516 memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
517 memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
519 /* CS4: External register chip select */
520 memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
521 memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
523 /* CS5: dummy for accurate delay */
524 memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
525 memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
527 ioport->iop_padat = PA_GP_OUTVAL;
528 ioport->iop_paodr = PA_ODR_VAL;
529 ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
530 ioport->iop_papar = PA_SP_MASK;
532 cpm->cp_pbdat = PB_GP_OUTVAL;
533 cpm->cp_pbodr = PB_ODR_VAL;
534 cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
535 cpm->cp_pbpar = PB_SP_MASK;
537 ioport->iop_pcdat = PC_GP_OUTVAL;
538 ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
539 ioport->iop_pcso = PC_SOVAL;
540 ioport->iop_pcint = PC_INTVAL;
541 ioport->iop_pcpar = PC_SP_MASK;
543 ioport->iop_pddat = PD_GP_OUTVAL;
544 ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL;
545 ioport->iop_pdpar = PD_SP_MASK;
547 /* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */
552 #if (CONFIG_COMMANDS & CFG_CMD_NAND)
554 #include <linux/mtd/nand.h>
556 extern ulong nand_probe(ulong physadr);
557 extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
561 unsigned long totlen = nand_probe(CFG_NAND_BASE);
563 printf ("%4lu MB\n", totlen >> 20);
567 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
569 int pcmcia_init(void)
578 * Returns 1 if keys pressed to start the power-on long-running tests
579 * Called from board_init_f().
581 int post_hotkeys_pressed(void)
583 return 0; /* No hotkeys supported */
587 #ifdef CONFIG_HW_WATCHDOG
589 void hw_watchdog_reset(void)
591 /* XXX add here the really funky stuff */