2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
10 * U-Boot port on NetTA4 board
18 #ifdef CONFIG_HW_WATCHDOG
22 int fec8xx_miiphy_read(char *devname, unsigned char addr,
23 unsigned char reg, unsigned short *value);
24 int fec8xx_miiphy_write(char *devname, unsigned char addr,
25 unsigned char reg, unsigned short value);
27 /****************************************************************/
29 /* some sane bit macros */
30 #define _BD(_b) (1U << (31-(_b)))
31 #define _BDR(_l, _h) (((((1U << (31-(_l))) - 1) << 1) | 1) & ~((1U << (31-(_h))) - 1))
33 #define _BW(_b) (1U << (15-(_b)))
34 #define _BWR(_l, _h) (((((1U << (15-(_l))) - 1) << 1) | 1) & ~((1U << (15-(_h))) - 1))
36 #define _BB(_b) (1U << (7-(_b)))
37 #define _BBR(_l, _h) (((((1U << (7-(_l))) - 1) << 1) | 1) & ~((1U << (7-(_h))) - 1))
39 #define _B(_b) _BD(_b)
40 #define _BR(_l, _h) _BDR(_l, _h)
42 /****************************************************************/
45 * Check Board Identity:
52 printf ("Intracom NETTA"
53 #if defined(CONFIG_NETTA_ISDN)
56 #if defined(CONFIG_NETTA_6412)
66 /****************************************************************/
68 #define _NOT_USED_ 0xFFFFFFFF
70 /****************************************************************/
72 #define CS_0000 0x00000000
73 #define CS_0001 0x10000000
74 #define CS_0010 0x20000000
75 #define CS_0011 0x30000000
76 #define CS_0100 0x40000000
77 #define CS_0101 0x50000000
78 #define CS_0110 0x60000000
79 #define CS_0111 0x70000000
80 #define CS_1000 0x80000000
81 #define CS_1001 0x90000000
82 #define CS_1010 0xA0000000
83 #define CS_1011 0xB0000000
84 #define CS_1100 0xC0000000
85 #define CS_1101 0xD0000000
86 #define CS_1110 0xE0000000
87 #define CS_1111 0xF0000000
89 #define BS_0000 0x00000000
90 #define BS_0001 0x01000000
91 #define BS_0010 0x02000000
92 #define BS_0011 0x03000000
93 #define BS_0100 0x04000000
94 #define BS_0101 0x05000000
95 #define BS_0110 0x06000000
96 #define BS_0111 0x07000000
97 #define BS_1000 0x08000000
98 #define BS_1001 0x09000000
99 #define BS_1010 0x0A000000
100 #define BS_1011 0x0B000000
101 #define BS_1100 0x0C000000
102 #define BS_1101 0x0D000000
103 #define BS_1110 0x0E000000
104 #define BS_1111 0x0F000000
106 #define A10_AAAA 0x00000000
107 #define A10_AAA0 0x00200000
108 #define A10_AAA1 0x00300000
109 #define A10_000A 0x00800000
110 #define A10_0000 0x00A00000
111 #define A10_0001 0x00B00000
112 #define A10_111A 0x00C00000
113 #define A10_1110 0x00E00000
114 #define A10_1111 0x00F00000
116 #define RAS_0000 0x00000000
117 #define RAS_0001 0x00040000
118 #define RAS_1110 0x00080000
119 #define RAS_1111 0x000C0000
121 #define CAS_0000 0x00000000
122 #define CAS_0001 0x00010000
123 #define CAS_1110 0x00020000
124 #define CAS_1111 0x00030000
126 #define WE_0000 0x00000000
127 #define WE_0001 0x00004000
128 #define WE_1110 0x00008000
129 #define WE_1111 0x0000C000
131 #define GPL4_0000 0x00000000
132 #define GPL4_0001 0x00001000
133 #define GPL4_1110 0x00002000
134 #define GPL4_1111 0x00003000
136 #define GPL5_0000 0x00000000
137 #define GPL5_0001 0x00000400
138 #define GPL5_1110 0x00000800
139 #define GPL5_1111 0x00000C00
140 #define LOOP 0x00000080
142 #define EXEN 0x00000040
144 #define AMX_COL 0x00000000
145 #define AMX_ROW 0x00000020
146 #define AMX_MAR 0x00000030
148 #define NA 0x00000008
150 #define UTA 0x00000004
152 #define TODT 0x00000002
154 #define LAST 0x00000001
156 /* #define CAS_LATENCY 3 */
157 #define CAS_LATENCY 2
159 const uint sdram_table[0x40] = {
163 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
164 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
165 CS_0000 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
166 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
167 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
168 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
169 _NOT_USED_, _NOT_USED_,
172 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
173 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
174 CS_0001 | BS_1111 | A10_0001 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
175 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
176 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
177 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
178 CS_0001 | BS_0001 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL, /* PALL */
179 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | TODT | LAST, /* NOP */
180 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
181 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
184 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
185 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
186 CS_0000 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
187 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
188 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
189 _NOT_USED_, _NOT_USED_, _NOT_USED_,
192 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
193 CS_1111 | BS_1111 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
194 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0000 | AMX_COL, /* WRITE */
195 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
196 CS_1111 | BS_0000 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
197 CS_1111 | BS_0001 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
198 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
199 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA, /* PALL */
200 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
201 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
202 _NOT_USED_, _NOT_USED_, _NOT_USED_,
207 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
208 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
209 CS_0001 | BS_0001 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
210 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
211 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
213 _NOT_USED_, _NOT_USED_,
216 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
217 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1111 | AMX_COL | UTA, /* NOP */
218 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_1111 | AMX_COL | UTA, /* READ */
219 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
220 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
221 CS_1111 | BS_0001 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
222 CS_1110 | BS_1111 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL, /* NOP */
223 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
225 _NOT_USED_, _NOT_USED_, _NOT_USED_,
226 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
229 CS_0001 | BS_1111 | A10_AAA0 | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
230 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
231 CS_0000 | BS_0001 | A10_0001 | RAS_1110 | CAS_0001 | WE_0000 | AMX_COL | UTA, /* WRITE */
232 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
234 _NOT_USED_, _NOT_USED_,
238 CS_0001 | BS_1111 | A10_AAAA | RAS_0001 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* ACT */
239 CS_1110 | BS_1110 | A10_0000 | RAS_1111 | CAS_1110 | WE_1110 | AMX_COL, /* NOP */
240 CS_0001 | BS_0000 | A10_0000 | RAS_1111 | CAS_0001 | WE_0001 | AMX_COL, /* WRITE */
241 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
242 CS_1111 | BS_0000 | A10_0000 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL, /* NOP */
243 CS_1110 | BS_0001 | A10_0001 | RAS_1110 | CAS_1111 | WE_1110 | AMX_COL | UTA, /* NOP */
244 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | TODT | LAST, /* PALL */
246 _NOT_USED_, _NOT_USED_, _NOT_USED_,
247 _NOT_USED_, _NOT_USED_, _NOT_USED_,
248 _NOT_USED_, _NOT_USED_,
253 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_0001 | WE_1111 | AMX_COL | UTA | LOOP, /* ATRFR */
254 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
255 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
256 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA, /* NOP */
257 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | LOOP, /* NOP */
258 CS_1111 | BS_1111 | A10_1111 | RAS_1111 | CAS_1111 | WE_1111 | AMX_COL | UTA | TODT | LAST, /* NOP */
259 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
260 _NOT_USED_, _NOT_USED_,
263 CS_0001 | BS_1111 | A10_1111 | RAS_0001 | CAS_1111 | WE_0001 | AMX_COL | UTA | LAST,
267 CS_1110 | BS_1111 | A10_1110 | RAS_1110 | CAS_1110 | WE_1110 | AMX_MAR | UTA,
268 CS_0001 | BS_1111 | A10_0001 | RAS_0001 | CAS_0001 | WE_0001 | AMX_MAR | UTA | LAST,
271 /* 0xC8 = 0b11001000 , CAS3, >> 2 = 0b00 11 0 010 */
272 /* 0x88 = 0b10001000 , CAS2, >> 2 = 0b00 10 0 010 */
273 #define MAR_SDRAM_INIT ((CAS_LATENCY << 6) | 0x00000008LU)
276 #define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
277 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
278 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
280 void check_ram(unsigned int addr, unsigned int size)
282 unsigned int i, j, v, vv;
283 volatile unsigned int *p;
286 p = (unsigned int *)addr;
287 pv = (unsigned int)p;
288 for (i = 0; i < size / sizeof(unsigned int); i++, pv += sizeof(unsigned int))
291 p = (unsigned int *)addr;
292 for (i = 0; i < size / sizeof(unsigned int); i++) {
296 printf("%p: read %08x instead of %08x\n", p, vv, v);
302 for (j = 0; j < 5; j++) {
304 case 0: v = 0x00000000; break;
305 case 1: v = 0xffffffff; break;
306 case 2: v = 0x55555555; break;
307 case 3: v = 0xaaaaaaaa; break;
308 default:v = 0xdeadbeef; break;
310 p = (unsigned int *)addr;
311 for (i = 0; i < size / sizeof(unsigned int); i++) {
315 printf("%p: read %08x instead of %08x\n", p, vv, v);
324 phys_size_t initdram(int board_type)
326 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
327 volatile memctl8xx_t *memctl = &immap->im_memctl;
330 upmconfig(UPMB, (uint *) sdram_table, sizeof(sdram_table) / sizeof(uint));
333 * Preliminary prescaler for refresh
335 memctl->memc_mptpr = MPTPR_PTP_DIV8;
337 memctl->memc_mar = MAR_SDRAM_INIT; /* 32-bit address to be output on the address bus if AMX = 0b11 */
340 * Map controller bank 3 to the SDRAM bank at preliminary address.
342 memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
343 memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
345 memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE; /* no refresh yet */
349 /* perform SDRAM initialisation sequence */
350 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3C); /* precharge all */
353 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(2) | MCR_MAD(0x30); /* refresh 2 times(0) */
356 memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x3E); /* exception program (write mar)*/
359 memctl->memc_mbmr |= MAMR_PTAE; /* enable refresh */
367 *(volatile u32 *)0 = d1;
368 d2 = *(volatile u32 *)0;
370 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
375 *(volatile u32 *)0 = d1;
376 d2 = *(volatile u32 *)0;
378 printf("DRAM fails: wrote 0x%08x read 0x%08x\n", d1, d2);
383 size = get_ram_size((long *)0, SDRAM_MAX_SIZE);
387 check_ram(( 0 << 20), (2 << 20));
388 printf("check 16\n");
389 check_ram((16 << 20), (2 << 20));
390 printf("check 32\n");
391 check_ram((32 << 20), (2 << 20));
392 printf("check 48\n");
393 check_ram((48 << 20), (2 << 20));
397 printf("SIZE is zero: LOOP on 0\n");
399 *(volatile u32 *)0 = 0;
400 (void)*(volatile u32 *)0;
407 /* ------------------------------------------------------------------------- */
409 int misc_init_r(void)
414 void reset_phys(void)
419 /* reset the damn phys */
422 for (phyno = 0; phyno < 32; ++phyno) {
423 fec8xx_miiphy_read(NULL, phyno, MII_PHYSID1, &v);
426 fec8xx_miiphy_write(NULL, phyno, MII_BMCR, BMCR_PDOWN);
428 fec8xx_miiphy_write(NULL, phyno, MII_BMCR,
429 BMCR_RESET | BMCR_ANENABLE);
434 extern int board_dsp_reset(void);
436 int last_stage_init(void)
441 r = board_dsp_reset();
443 printf("*** WARNING *** DSP reset failed (run diagnostics)\n");
447 /* ------------------------------------------------------------------------- */
449 /* GP = general purpose, SP = special purpose (on chip peripheral) */
451 /* bits that can have a special purpose or can be configured as inputs/outputs */
452 #define PA_GP_INMASK (_BWR(3) | _BWR(7, 9) | _BW(11))
453 #define PA_GP_OUTMASK (_BW(6) | _BW(10) | _BWR(12, 15))
454 #define PA_SP_MASK (_BWR(0, 2) | _BWR(4, 5))
456 #define PA_GP_OUTVAL (_BW(13) | _BWR(14, 15))
457 #define PA_SP_DIRVAL 0
459 #define PB_GP_INMASK (_B(28) | _B(31))
460 #define PB_GP_OUTMASK (_BR(15, 19) | _BR(26, 27) | _BR(29, 30))
461 #define PB_SP_MASK (_BR(22, 25))
463 #define PB_GP_OUTVAL (_BR(15, 19) | _BR(26, 27) | _BR(29, 31))
464 #define PB_SP_DIRVAL 0
466 #define PC_GP_INMASK (_BW(5) | _BW(7) | _BW(8) | _BWR(9, 11) | _BWR(13, 15))
467 #define PC_GP_OUTMASK (_BW(6) | _BW(12))
468 #define PC_SP_MASK (_BW(4) | _BW(8))
470 #define PC_INTVAL _BW(7)
471 #define PC_GP_OUTVAL (_BW(6) | _BW(12))
472 #define PC_SP_DIRVAL 0
474 #define PD_GP_INMASK 0
475 #define PD_GP_OUTMASK _BWR(3, 15)
478 #if defined(CONFIG_NETTA_6412)
480 #define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11) | _BW(15))
484 #define PD_GP_OUTVAL (_BWR(5, 7) | _BW(9) | _BW(11))
488 #define PD_SP_DIRVAL 0
490 int board_early_init_f(void)
492 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
493 volatile iop8xx_t *ioport = &immap->im_ioport;
494 volatile cpm8xx_t *cpm = &immap->im_cpm;
495 volatile memctl8xx_t *memctl = &immap->im_memctl;
497 /* CS1: NAND chip select */
498 memctl->memc_or1 = ((0xFFFFFFFFLU & ~(NAND_SIZE - 1)) | OR_BI | OR_SCY_2_CLK | OR_TRLX | OR_ACS_DIV2) ;
499 memctl->memc_br1 = ((NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
500 #if !defined(CONFIG_NETTA_6412)
502 memctl->memc_or2 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
503 memctl->memc_br2 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
506 memctl->memc_or6 = ((0xFFFFFFFFLU & ~(DSP_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_7_CLK | OR_ACS_DIV2);
507 memctl->memc_br6 = ((DSP_BASE & BR_BA_MSK) | BR_PS_16 | BR_V);
509 /* CS4: External register chip select */
510 memctl->memc_or4 = ((0xFFFFFFFFLU & ~(ER_SIZE - 1)) | OR_BI | OR_SCY_4_CLK);
511 memctl->memc_br4 = ((ER_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
513 /* CS5: dummy for accurate delay */
514 memctl->memc_or5 = ((0xFFFFFFFFLU & ~(DUMMY_SIZE - 1)) | OR_CSNT_SAM | OR_BI | OR_SCY_0_CLK | OR_ACS_DIV2);
515 memctl->memc_br5 = ((DUMMY_BASE & BR_BA_MSK) | BR_PS_32 | BR_V);
517 ioport->iop_padat = PA_GP_OUTVAL;
518 ioport->iop_paodr = PA_ODR_VAL;
519 ioport->iop_padir = PA_GP_OUTMASK | PA_SP_DIRVAL;
520 ioport->iop_papar = PA_SP_MASK;
522 cpm->cp_pbdat = PB_GP_OUTVAL;
523 cpm->cp_pbodr = PB_ODR_VAL;
524 cpm->cp_pbdir = PB_GP_OUTMASK | PB_SP_DIRVAL;
525 cpm->cp_pbpar = PB_SP_MASK;
527 ioport->iop_pcdat = PC_GP_OUTVAL;
528 ioport->iop_pcdir = PC_GP_OUTMASK | PC_SP_DIRVAL;
529 ioport->iop_pcso = PC_SOVAL;
530 ioport->iop_pcint = PC_INTVAL;
531 ioport->iop_pcpar = PC_SP_MASK;
533 ioport->iop_pddat = PD_GP_OUTVAL;
534 ioport->iop_pddir = PD_GP_OUTMASK | PD_SP_DIRVAL;
535 ioport->iop_pdpar = PD_SP_MASK;
537 /* ioport->iop_pddat |= (1 << (15 - 6)) | (1 << (15 - 7)); */
542 #if defined(CONFIG_CMD_PCMCIA)
544 int pcmcia_init(void)
551 #ifdef CONFIG_HW_WATCHDOG
553 void hw_watchdog_reset(void)
555 /* XXX add here the really funky stuff */