3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
5 * (C) Copyright 2001-2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 /* ------------------------------------------------------------------------- */
33 static long int dram_size (long int, long int *, long int);
35 /* ------------------------------------------------------------------------- */
37 #define _NOT_USED_ 0xFFFFFFFF
39 const uint sdram_table[] = {
40 #if (MPC8XX_SPEED <= 50000000L)
42 * Single Read. (Offset 0 in UPMA RAM)
44 0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
48 * SDRAM Initialization (offset 5 in UPMA RAM)
50 * This is no UPM entry point. The following definition uses
51 * the remaining space to establish an initialization
52 * sequence, which is executed by a RUN command.
55 0x1FE7F434, 0xEFABE834, 0x1FA7D435,
58 * Burst Read. (Offset 8 in UPMA RAM)
60 0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
61 0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
62 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
63 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
66 * Single Write. (Offset 18 in UPMA RAM)
68 0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
69 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
72 * Burst Write. (Offset 20 in UPMA RAM)
74 0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
75 0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
76 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
77 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
80 * Refresh (Offset 30 in UPMA RAM)
82 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
83 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
84 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
87 * Exception. (Offset 3c in UPMA RAM)
89 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
93 * Single Read. (Offset 0 in UPMA RAM)
95 0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
99 * SDRAM Initialization (offset 5 in UPMA RAM)
101 * This is no UPM entry point. The following definition uses
102 * the remaining space to establish an initialization
103 * sequence, which is executed by a RUN command.
106 0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
109 * Burst Read. (Offset 8 in UPMA RAM)
111 0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
112 0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
113 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
114 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
117 * Single Write. (Offset 18 in UPMA RAM)
119 0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
120 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
123 * Burst Write. (Offset 20 in UPMA RAM)
125 0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
126 0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
127 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
128 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
131 * Refresh (Offset 30 in UPMA RAM)
133 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
134 0xFFFFFC84, 0xFFFFFC07,
135 _NOT_USED_, _NOT_USED_, _NOT_USED_,
136 _NOT_USED_, _NOT_USED_, _NOT_USED_,
139 * Exception. (Offset 3c in UPMA RAM)
141 0x7FFFFC07, /* last */
142 _NOT_USED_, _NOT_USED_, _NOT_USED_,
146 /* ------------------------------------------------------------------------- */
150 * Check Board Identity:
154 int checkboard (void)
156 printf ("Board: Nexus NX823");
160 /* ------------------------------------------------------------------------- */
162 long int initdram (int board_type)
164 volatile immap_t *immap = (immap_t *) CFG_IMMR;
165 volatile memctl8xx_t *memctl = &immap->im_memctl;
166 long int size_b0, size_b1, size8, size9;
168 upmconfig (UPMA, (uint *) sdram_table,
169 sizeof (sdram_table) / sizeof (uint));
172 * Up to 2 Banks of 64Mbit x 2 devices
173 * Initial builds only have 1
175 memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
176 memctl->memc_mar = 0x00000088;
179 * Map controller SDRAM bank 0
181 memctl->memc_or1 = CFG_OR1_PRELIM;
182 memctl->memc_br1 = CFG_BR1_PRELIM;
183 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
187 * Map controller SDRAM bank 1
189 memctl->memc_or2 = CFG_OR2_PRELIM;
190 memctl->memc_br2 = CFG_BR2_PRELIM;
193 * Perform SDRAM initializsation sequence
195 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
197 memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
200 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
202 memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */
205 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
209 * Preliminary prescaler for refresh (depends on number of
210 * banks): This value is selected for four cycles every 62.4 us
211 * with two SDRAM banks or four cycles every 31.2 us with one
212 * bank. It will be adjusted after memory sizing.
214 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
216 memctl->memc_mar = 0x00000088;
220 * Check Bank 0 Memory Size for re-configuration
224 size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
232 size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE1_PRELIM,
235 if (size8 < size9) { /* leave configuration at 9 columns */
237 /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
238 } else { /* back to 8 columns */
240 memctl->memc_mamr = CFG_MAMR_8COL;
242 /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
246 * Check Bank 1 Memory Size
247 * use current column settings
248 * [9 column SDRAM may also be used in 8 column mode,
249 * but then only half the real size will be used.]
251 size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE2_PRELIM,
253 /* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
258 * Adjust refresh rate depending on SDRAM type, both banks
259 * For types > 128 MBit leave it at the current (fast) rate
261 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
262 /* reduce to 15.6 us (62.4 us / quad) */
263 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
268 * Final mapping: map bigger bank first
270 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
273 ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
275 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
279 * Position Bank 0 immediately above Bank 1
282 ((-size_b0) & 0xFFFF0000) |
285 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
296 memctl->memc_br1 = 0;
298 /* adjust refresh rate depending on SDRAM type, one bank */
299 reg = memctl->memc_mptpr;
300 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
301 memctl->memc_mptpr = reg;
304 } else { /* SDRAM Bank 0 is bigger - map first */
307 ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
309 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
313 * Position Bank 1 immediately above Bank 0
316 ((-size_b1) & 0xFFFF0000) |
319 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
330 memctl->memc_br2 = 0;
332 /* adjust refresh rate depending on SDRAM type, one bank */
333 reg = memctl->memc_mptpr;
334 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
335 memctl->memc_mptpr = reg;
341 return (size_b0 + size_b1);
344 /* ------------------------------------------------------------------------- */
347 * Check memory range for valid RAM. A simple memory test determines
348 * the actually available RAM size between addresses `base' and
349 * `base + maxsize'. Some (not all) hardware errors are detected:
350 * - short between address lines
351 * - short between data lines
354 static long int dram_size (long int mamr_value, long int *base,
357 volatile immap_t *immap = (immap_t *) CFG_IMMR;
358 volatile memctl8xx_t *memctl = &immap->im_memctl;
360 memctl->memc_mamr = mamr_value;
362 return (get_ram_size (base, maxsize));
367 int misc_init_r (void)
369 DECLARE_GLOBAL_DATA_PTR;
372 u_char *e = gd->bd->bi_enetaddr;
374 /* save serial numbre from flash (uniquely programmed) */
375 my_sernum = malloc (8);
376 memcpy (my_sernum, gd->bd->bi_sernum, 8);
378 /* save env variables according to sernum */
379 sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
380 setenv ("serial#", tmp);
382 sprintf (tmp, "%02x:%02x:%02x:%02x:%02x:%02x", e[0], e[1], e[2], e[3],
384 setenv ("ethaddr", tmp);
388 void load_sernum_ethaddr (void)
390 DECLARE_GLOBAL_DATA_PTR;
395 for (i = 0; i < 8; i++) {
396 bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i);
398 bd->bi_enetaddr[0] = 0x10;
399 bd->bi_enetaddr[1] = 0x20;
400 bd->bi_enetaddr[2] = 0x30;
401 bd->bi_enetaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
402 bd->bi_enetaddr[4] = bd->bi_sernum[5];
403 bd->bi_enetaddr[5] = bd->bi_sernum[6];