3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
5 * (C) Copyright 2001-2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * SPDX-License-Identifier: GPL-2.0+
16 DECLARE_GLOBAL_DATA_PTR;
18 static long int dram_size (long int, long int *, long int);
20 #define _NOT_USED_ 0xFFFFFFFF
22 const uint sdram_table[] = {
23 #if (MPC8XX_SPEED <= 50000000L)
25 * Single Read. (Offset 0 in UPMA RAM)
27 0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
31 * SDRAM Initialization (offset 5 in UPMA RAM)
33 * This is no UPM entry point. The following definition uses
34 * the remaining space to establish an initialization
35 * sequence, which is executed by a RUN command.
38 0x1FE7F434, 0xEFABE834, 0x1FA7D435,
41 * Burst Read. (Offset 8 in UPMA RAM)
43 0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
44 0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
45 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
46 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
49 * Single Write. (Offset 18 in UPMA RAM)
51 0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
52 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
55 * Burst Write. (Offset 20 in UPMA RAM)
57 0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
58 0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
59 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
60 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
63 * Refresh (Offset 30 in UPMA RAM)
65 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
66 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
67 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
70 * Exception. (Offset 3c in UPMA RAM)
72 0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
76 * Single Read. (Offset 0 in UPMA RAM)
78 0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
82 * SDRAM Initialization (offset 5 in UPMA RAM)
84 * This is no UPM entry point. The following definition uses
85 * the remaining space to establish an initialization
86 * sequence, which is executed by a RUN command.
89 0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
92 * Burst Read. (Offset 8 in UPMA RAM)
94 0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
95 0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
96 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
97 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
100 * Single Write. (Offset 18 in UPMA RAM)
102 0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
103 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
106 * Burst Write. (Offset 20 in UPMA RAM)
108 0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
109 0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
110 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
111 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
114 * Refresh (Offset 30 in UPMA RAM)
116 0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
117 0xFFFFFC84, 0xFFFFFC07,
118 _NOT_USED_, _NOT_USED_, _NOT_USED_,
119 _NOT_USED_, _NOT_USED_, _NOT_USED_,
122 * Exception. (Offset 3c in UPMA RAM)
124 0x7FFFFC07, /* last */
125 _NOT_USED_, _NOT_USED_, _NOT_USED_,
129 /* ------------------------------------------------------------------------- */
133 * Check Board Identity:
137 int checkboard (void)
139 printf ("Board: Nexus NX823");
143 /* ------------------------------------------------------------------------- */
145 phys_size_t initdram (int board_type)
147 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
148 volatile memctl8xx_t *memctl = &immap->im_memctl;
149 long int size_b0, size_b1, size8, size9;
151 upmconfig (UPMA, (uint *) sdram_table,
152 sizeof (sdram_table) / sizeof (uint));
155 * Up to 2 Banks of 64Mbit x 2 devices
156 * Initial builds only have 1
158 memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
159 memctl->memc_mar = 0x00000088;
162 * Map controller SDRAM bank 0
164 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
165 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
166 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
170 * Map controller SDRAM bank 1
172 memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
173 memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
176 * Perform SDRAM initializsation sequence
178 memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
180 memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - execute twice */
183 memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
185 memctl->memc_mcr = 0x80004230; /* SDRAM bank 1 - execute twice */
188 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
192 * Preliminary prescaler for refresh (depends on number of
193 * banks): This value is selected for four cycles every 62.4 us
194 * with two SDRAM banks or four cycles every 31.2 us with one
195 * bank. It will be adjusted after memory sizing.
197 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
199 memctl->memc_mar = 0x00000088;
203 * Check Bank 0 Memory Size for re-configuration
207 size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
215 size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
218 if (size8 < size9) { /* leave configuration at 9 columns */
220 /* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
221 } else { /* back to 8 columns */
223 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
225 /* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
229 * Check Bank 1 Memory Size
230 * use current column settings
231 * [9 column SDRAM may also be used in 8 column mode,
232 * but then only half the real size will be used.]
234 size_b1 = dram_size (memctl->memc_mamr, (long *) SDRAM_BASE2_PRELIM,
236 /* debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20); */
241 * Adjust refresh rate depending on SDRAM type, both banks
242 * For types > 128 MBit leave it at the current (fast) rate
244 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
245 /* reduce to 15.6 us (62.4 us / quad) */
246 memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
251 * Final mapping: map bigger bank first
253 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
256 ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
258 (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
262 * Position Bank 0 immediately above Bank 1
265 ((-size_b0) & 0xFFFF0000) |
266 CONFIG_SYS_OR_TIMING_SDRAM;
268 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
279 memctl->memc_br1 = 0;
281 /* adjust refresh rate depending on SDRAM type, one bank */
282 reg = memctl->memc_mptpr;
283 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
284 memctl->memc_mptpr = reg;
287 } else { /* SDRAM Bank 0 is bigger - map first */
290 ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
292 (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
296 * Position Bank 1 immediately above Bank 0
299 ((-size_b1) & 0xFFFF0000) |
300 CONFIG_SYS_OR_TIMING_SDRAM;
302 ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
313 memctl->memc_br2 = 0;
315 /* adjust refresh rate depending on SDRAM type, one bank */
316 reg = memctl->memc_mptpr;
317 reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
318 memctl->memc_mptpr = reg;
324 return (size_b0 + size_b1);
327 /* ------------------------------------------------------------------------- */
330 * Check memory range for valid RAM. A simple memory test determines
331 * the actually available RAM size between addresses `base' and
332 * `base + maxsize'. Some (not all) hardware errors are detected:
333 * - short between address lines
334 * - short between data lines
337 static long int dram_size (long int mamr_value, long int *base,
340 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
341 volatile memctl8xx_t *memctl = &immap->im_memctl;
343 memctl->memc_mamr = mamr_value;
345 return (get_ram_size (base, maxsize));
348 int misc_init_r (void)
354 ulong *my_sernum = (unsigned long *)&bd->bi_sernum;
356 /* load unique serial number */
357 for (i = 0; i < 8; ++i)
358 bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i);
360 /* save env variables according to sernum */
361 sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
362 setenv ("serial#", tmp);
364 if (!eth_getenv_enetaddr("ethaddr", ethaddr)) {
368 ethaddr[3] = bd->bi_sernum[1] << 4 | bd->bi_sernum[2];
369 ethaddr[4] = bd->bi_sernum[5];
370 ethaddr[5] = bd->bi_sernum[6];