git.sur5r.net Git - u-boot/blob - board/ocotea/ocotea.c

   1 /*
   2  *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23
  24 #include <common.h>
  25 #include "ocotea.h"
  26 #include <asm/processor.h>
  27 #include <spd_sdram.h>
  28 #include <440gx_enet.h>
  29
  30 #define BOOT_SMALL_FLASH        32      /* 00100000 */
  31 #define FLASH_ONBD_N            2       /* 00000010 */
  32 #define FLASH_SRAM_SEL          1       /* 00000001 */
  33
  34 long int fixed_sdram (void);
  35 void fpga_init (void);
  36
  37 int board_early_init_f (void)
  38 {
  39         unsigned long mfr;
  40         unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
  41         unsigned char switch_status;
  42         unsigned long cs0_base;
  43         unsigned long cs0_size;
  44         unsigned long cs0_twt;
  45         unsigned long cs2_base;
  46         unsigned long cs2_size;
  47         unsigned long cs2_twt;
  48
  49         /*-------------------------------------------------------------------------+
  50           | Initialize EBC CONFIG
  51           +-------------------------------------------------------------------------*/
  52         mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
  53               EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
  54               EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
  55               EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
  56               EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
  57
  58         /*-------------------------------------------------------------------------+
  59           | FPGA. Initialize bank 7 with default values.
  60           +-------------------------------------------------------------------------*/
  61         mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
  62               EBC_BXAP_BCE_DISABLE|
  63               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  64               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  65               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
  66               EBC_BXAP_BEM_WRITEONLY|
  67               EBC_BXAP_PEN_DISABLED);
  68         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
  69               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
  70
  71         /* read FPGA base register FPGA_REG0 */
  72         switch_status = *fpga_base;
  73
  74         if (switch_status & 0x40) {
  75                 cs0_base = 0xFFE00000;
  76                 cs0_size = EBC_BXCR_BS_2MB;
  77                 cs0_twt = 8;
  78                 cs2_base = 0xFF800000;
  79                 cs2_size = EBC_BXCR_BS_4MB;
  80                 cs2_twt = 10;
  81         } else {
  82                 cs0_base = 0xFFC00000;
  83                 cs0_size = EBC_BXCR_BS_4MB;
  84                 cs0_twt = 10;
  85                 cs2_base = 0xFF800000;
  86                 cs2_size = EBC_BXCR_BS_2MB;
  87                 cs2_twt = 8;
  88         }
  89
  90         /*-------------------------------------------------------------------------+
  91           | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
  92           +-------------------------------------------------------------------------*/
  93         mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
  94               EBC_BXAP_BCE_DISABLE|
  95               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  96               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  97               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
  98               EBC_BXAP_BEM_WRITEONLY|
  99               EBC_BXAP_PEN_DISABLED);
 100         mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|
 101               cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 102
 103         /*-------------------------------------------------------------------------+
 104           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
 105           +-------------------------------------------------------------------------*/
 106         mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
 107               EBC_BXAP_BCE_DISABLE|
 108               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 109               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 110               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 111               EBC_BXAP_BEM_WRITEONLY|
 112               EBC_BXAP_PEN_DISABLED);
 113         mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
 114               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 115
 116         /*-------------------------------------------------------------------------+
 117           | 4 MB FLASH. Initialize bank 2 with default values.
 118           +-------------------------------------------------------------------------*/
 119         mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
 120               EBC_BXAP_BCE_DISABLE|
 121               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 122               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 123               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 124               EBC_BXAP_BEM_WRITEONLY|
 125               EBC_BXAP_PEN_DISABLED);
 126         mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|
 127               cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 128
 129         /*-------------------------------------------------------------------------+
 130           | FPGA. Initialize bank 7 with default values.
 131           +-------------------------------------------------------------------------*/
 132         mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
 133               EBC_BXAP_BCE_DISABLE|
 134               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 135               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 136               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 137               EBC_BXAP_BEM_WRITEONLY|
 138               EBC_BXAP_PEN_DISABLED);
 139         mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
 140               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 141
 142         /*--------------------------------------------------------------------
 143          * Setup the interrupt controller polarities, triggers, etc.
 144          *-------------------------------------------------------------------*/
 145         mtdcr (uic0sr, 0xffffffff);     /* clear all */
 146         mtdcr (uic0er, 0x00000000);     /* disable all */
 147         mtdcr (uic0cr, 0x00000009);     /* SMI & UIC1 crit are critical */
 148         mtdcr (uic0pr, 0xfffffe13);     /* per ref-board manual */
 149         mtdcr (uic0tr, 0x01c00008);     /* per ref-board manual */
 150         mtdcr (uic0vr, 0x00000001);     /* int31 highest, base=0x000 */
 151         mtdcr (uic0sr, 0xffffffff);     /* clear all */
 152
 153         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 154         mtdcr (uic1er, 0x00000000);     /* disable all */
 155         mtdcr (uic1cr, 0x00000000);     /* all non-critical */
 156         mtdcr (uic1pr, 0xffffe0ff);     /* per ref-board manual */
 157         mtdcr (uic1tr, 0x00ffc000);     /* per ref-board manual */
 158         mtdcr (uic1vr, 0x00000001);     /* int31 highest, base=0x000 */
 159         mtdcr (uic1sr, 0xffffffff);     /* clear all */
 160
 161         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 162         mtdcr (uic2er, 0x00000000);     /* disable all */
 163         mtdcr (uic2cr, 0x00000000);     /* all non-critical */
 164         mtdcr (uic2pr, 0xffffffff);     /* per ref-board manual */
 165         mtdcr (uic2tr, 0x00ff8c0f);     /* per ref-board manual */
 166         mtdcr (uic2vr, 0x00000001);     /* int31 highest, base=0x000 */
 167         mtdcr (uic2sr, 0xffffffff);     /* clear all */
 168
 169         mtdcr (uicb0sr, 0xfc000000); /* clear all */
 170         mtdcr (uicb0er, 0x00000000); /* disable all */
 171         mtdcr (uicb0cr, 0x00000000); /* all non-critical */
 172         mtdcr (uicb0pr, 0xfc000000); /* */
 173         mtdcr (uicb0tr, 0x00000000); /* */
 174         mtdcr (uicb0vr, 0x00000001); /* */
 175         mfsdr (sdr_mfr, mfr);
 176         mfr &= ~SDR0_MFR_ECS_MASK;
 177 /*      mtsdr(sdr_mfr, mfr); */
 178         fpga_init();
 179
 180         return 0;
 181 }
 182
 183
 184 int checkboard (void)
 185 {
 186         sys_info_t sysinfo;
 187
 188         get_sys_info (&sysinfo);
 189
 190         printf ("Board: IBM 440GX Evaluation Board\n");
 191         printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
 192         printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 193         printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
 194         printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
 195         printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
 196         return (0);
 197 }
 198
 199
 200 long int initdram (int board_type)
 201 {
 202         long dram_size = 0;
 203
 204 #if defined(CONFIG_SPD_EEPROM)
 205         dram_size = spd_sdram (0);
 206 #else
 207         dram_size = fixed_sdram ();
 208 #endif
 209         return dram_size;
 210 }
 211
 212
 213 #if defined(CFG_DRAM_TEST)
 214 int testdram (void)
 215 {
 216         uint *pstart = (uint *) 0x00000000;
 217         uint *pend = (uint *) 0x08000000;
 218         uint *p;
 219
 220         for (p = pstart; p < pend; p++)
 221                 *p = 0xaaaaaaaa;
 222
 223         for (p = pstart; p < pend; p++) {
 224                 if (*p != 0xaaaaaaaa) {
 225                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 226                         return 1;
 227                 }
 228         }
 229
 230         for (p = pstart; p < pend; p++)
 231                 *p = 0x55555555;
 232
 233         for (p = pstart; p < pend; p++) {
 234                 if (*p != 0x55555555) {
 235                         printf ("SDRAM test fails at: %08x\n", (uint) p);
 236                         return 1;
 237                 }
 238         }
 239         return 0;
 240 }
 241 #endif
 242
 243 #if !defined(CONFIG_SPD_EEPROM)
 244 /*************************************************************************
 245  *  fixed sdram init -- doesn't use serial presence detect.
 246  *
 247  *  Assumes:    128 MB, non-ECC, non-registered
 248  *              PLB @ 133 MHz
 249  *
 250  ************************************************************************/
 251 long int fixed_sdram (void)
 252 {
 253         uint reg;
 254
 255         /*--------------------------------------------------------------------
 256          * Setup some default
 257          *------------------------------------------------------------------*/
 258         mtsdram (mem_uabba, 0x00000000);        /* ubba=0 (default)             */
 259         mtsdram (mem_slio, 0x00000000);         /* rdre=0 wrre=0 rarw=0         */
 260         mtsdram (mem_devopt, 0x00000000);       /* dll=0 ds=0 (normal)          */
 261         mtsdram (mem_wddctr, 0x00000000);       /* wrcp=0 dcd=0                 */
 262         mtsdram (mem_clktr, 0x40000000);        /* clkp=1 (90 deg wr) dcdt=0    */
 263
 264         /*--------------------------------------------------------------------
 265          * Setup for board-specific specific mem
 266          *------------------------------------------------------------------*/
 267         /*
 268          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 269          */
 270         mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
 271         mtsdram (mem_tr0, 0x410a4012);  /* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
 272         /* RA=10 RD=3                       */
 273         mtsdram (mem_tr1, 0x8080082f);  /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
 274         mtsdram (mem_rtr, 0x08200000);  /* Rate 15.625 ns @ 133 MHz PLB     */
 275         mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM    */
 276         udelay (400);                   /* Delay 200 usecs (min)            */
 277
 278         /*--------------------------------------------------------------------
 279          * Enable the controller, then wait for DCEN to complete
 280          *------------------------------------------------------------------*/
 281         mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit           */
 282         for (;;) {
 283                 mfsdram (mem_mcsts, reg);
 284                 if (reg & 0x80000000)
 285                         break;
 286         }
 287
 288         return (128 * 1024 * 1024);     /* 128 MB                           */
 289 }
 290 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 291
 292
 293 /*************************************************************************
 294  *  pci_pre_init
 295  *
 296  *  This routine is called just prior to registering the hose and gives
 297  *  the board the opportunity to check things. Returning a value of zero
 298  *  indicates that things are bad & PCI initialization should be aborted.
 299  *
 300  *      Different boards may wish to customize the pci controller structure
 301  *      (add regions, override default access routines, etc) or perform
 302  *      certain pre-initialization actions.
 303  *
 304  ************************************************************************/
 305 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
 306 int pci_pre_init(struct pci_controller * hose )
 307 {
 308         unsigned long strap;
 309
 310         /*--------------------------------------------------------------------------+
 311          *      The ocotea board is always configured as the host & requires the
 312          *      PCI arbiter to be enabled.
 313          *--------------------------------------------------------------------------*/
 314         mfsdr(sdr_sdstp1, strap);
 315         if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
 316                 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
 317                 return 0;
 318         }
 319
 320         return 1;
 321 }
 322 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
 323
 324 /*************************************************************************
 325  *  pci_target_init
 326  *
 327  *      The bootstrap configuration provides default settings for the pci
 328  *      inbound map (PIM). But the bootstrap config choices are limited and
 329  *      may not be sufficient for a given board.
 330  *
 331  ************************************************************************/
 332 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 333 void pci_target_init(struct pci_controller * hose )
 334 {
 335         DECLARE_GLOBAL_DATA_PTR;
 336
 337         /*--------------------------------------------------------------------------+
 338          * Disable everything
 339          *--------------------------------------------------------------------------*/
 340         out32r( PCIX0_PIM0SA, 0 ); /* disable */
 341         out32r( PCIX0_PIM1SA, 0 ); /* disable */
 342         out32r( PCIX0_PIM2SA, 0 ); /* disable */
 343         out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
 344
 345         /*--------------------------------------------------------------------------+
 346          * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 347          * options to not support sizes such as 128/256 MB.
 348          *--------------------------------------------------------------------------*/
 349         out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
 350         out32r( PCIX0_PIM0LAH, 0 );
 351         out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 352
 353         out32r( PCIX0_BAR0, 0 );
 354
 355         /*--------------------------------------------------------------------------+
 356          * Program the board's subsystem id/vendor id
 357          *--------------------------------------------------------------------------*/
 358         out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
 359         out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
 360
 361         out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 362 }
 363 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 364
 365
 366 /*************************************************************************
 367  *  is_pci_host
 368  *
 369  *      This routine is called to determine if a pci scan should be
 370  *      performed. With various hardware environments (especially cPCI and
 371  *      PPMC) it's insufficient to depend on the state of the arbiter enable
 372  *      bit in the strap register, or generic host/adapter assumptions.
 373  *
 374  *      Rather than hard-code a bad assumption in the general 440 code, the
 375  *      440 pci code requires the board to decide at runtime.
 376  *
 377  *      Return 0 for adapter mode, non-zero for host (monarch) mode.
 378  *
 379  *
 380  ************************************************************************/
 381 #if defined(CONFIG_PCI)
 382 int is_pci_host(struct pci_controller *hose)
 383 {
 384     /* The ocotea board is always configured as host. */
 385     return(1);
 386 }
 387 #endif /* defined(CONFIG_PCI) */
 388
 389
 390 void fpga_init(void)
 391 {
 392         unsigned long group;
 393         unsigned long sdr0_pfc0;
 394         unsigned long sdr0_pfc1;
 395         unsigned long sdr0_cust0;
 396         unsigned long pvr;
 397
 398         mfsdr (sdr_pfc0, sdr0_pfc0);
 399         mfsdr (sdr_pfc1, sdr0_pfc1);
 400         group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
 401         pvr = get_pvr ();
 402
 403         sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
 404         if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
 405                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
 406                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
 407                 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 408                      FPGA_REG2_EXT_INTFACE_ENABLE);
 409                 mtsdr (sdr_pfc0, sdr0_pfc0);
 410                 mtsdr (sdr_pfc1, sdr0_pfc1);
 411         } else {
 412                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
 413                 switch (group)
 414                 {
 415                 case 0:
 416                 case 1:
 417                 case 2:
 418                         /* CPU trace A */
 419                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 420                              FPGA_REG2_EXT_INTFACE_ENABLE);
 421                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
 422                         mtsdr (sdr_pfc0, sdr0_pfc0);
 423                         mtsdr (sdr_pfc1, sdr0_pfc1);
 424                         break;
 425                 case 3:
 426                 case 4:
 427                 case 5:
 428                 case 6:
 429                         /* CPU trace B - Over EBMI */
 430                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
 431                         mtsdr (sdr_pfc0, sdr0_pfc0);
 432                         mtsdr (sdr_pfc1, sdr0_pfc1);
 433                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 434                              FPGA_REG2_EXT_INTFACE_DISABLE);
 435                         break;
 436                 }
 437         }
 438
 439         /* Initialize the ethernet specific functions in the fpga */
 440         mfsdr(sdr_pfc1, sdr0_pfc1);
 441         mfsdr(sdr_cust0, sdr0_cust0);
 442         if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
 443             ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
 444              (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
 445         {
 446                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 447                 {
 448                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
 449                              FPGA_REG3_ENET_GROUP7);
 450                 }
 451                 else
 452                 {
 453                         if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
 454                         {
 455                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 456                                      FPGA_REG3_ENET_GROUP7);
 457                         }
 458                         else
 459                         {
 460                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 461                                      FPGA_REG3_ENET_GROUP8);
 462                         }
 463                 }
 464         }
 465         else
 466         {
 467                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 468                 {
 469                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
 470                              FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
 471                 }
 472                 else
 473                 {
 474                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 475                              FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
 476                 }
 477         }
 478         out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
 479              FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
 480              FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
 481
 482         /* reset the gigabyte phy if necessary */
 483         if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
 484         {
 485                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 486                 {
 487                         out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
 488                         udelay(10000);
 489                         out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
 490                 }
 491                 else
 492                 {
 493                         out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
 494                         udelay(10000);
 495                         out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
 496                 }
 497         }
 498
 499         /* Turn off the LED's */
 500         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
 501              FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
 502              FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
 503
 504         return;
 505 }
 506
 507 #ifdef CONFIG_POST
 508 /*
 509  * Returns 1 if keys pressed to start the power-on long-running tests
 510  * Called from board_init_f().
 511  */
 512 int post_hotkeys_pressed(void)
 513 {
 514
 515         return (ctrlc());
 516 }
 517 #endif