2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
7 * -- Some bits of code used from rrload's head_OMAP1510.s --
8 * Copyright (C) 2002 RidgeRun, Inc.
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if defined(CONFIG_OMAP1510)
33 #include <./configs/omap1510.h>
36 #define OMAP1510_CLKS ((1<<EN_XORPCK)|(1<<EN_PERCK)|(1<<EN_TIMCK)|(1<<EN_GPIOCK))
40 .word TEXT_BASE /* sdram load addr from config.mk */
46 * Configure 1510 pins functions to match our board.
48 ldr r0, REG_PULL_DWN_CTRL_0
49 ldr r1, VAL_PULL_DWN_CTRL_0
51 ldr r0, REG_PULL_DWN_CTRL_1
52 ldr r1, VAL_PULL_DWN_CTRL_1
54 ldr r0, REG_PULL_DWN_CTRL_2
55 ldr r1, VAL_PULL_DWN_CTRL_2
57 ldr r0, REG_PULL_DWN_CTRL_3
58 ldr r1, VAL_PULL_DWN_CTRL_3
60 ldr r0, REG_FUNC_MUX_CTRL_4
61 ldr r1, VAL_FUNC_MUX_CTRL_4
63 ldr r0, REG_FUNC_MUX_CTRL_5
64 ldr r1, VAL_FUNC_MUX_CTRL_5
66 ldr r0, REG_FUNC_MUX_CTRL_6
67 ldr r1, VAL_FUNC_MUX_CTRL_6
69 ldr r0, REG_FUNC_MUX_CTRL_7
70 ldr r1, VAL_FUNC_MUX_CTRL_7
72 ldr r0, REG_FUNC_MUX_CTRL_8
73 ldr r1, VAL_FUNC_MUX_CTRL_8
75 ldr r0, REG_FUNC_MUX_CTRL_9
76 ldr r1, VAL_FUNC_MUX_CTRL_9
78 ldr r0, REG_FUNC_MUX_CTRL_A
79 ldr r1, VAL_FUNC_MUX_CTRL_A
81 ldr r0, REG_FUNC_MUX_CTRL_B
82 ldr r1, VAL_FUNC_MUX_CTRL_B
84 ldr r0, REG_FUNC_MUX_CTRL_C
85 ldr r1, VAL_FUNC_MUX_CTRL_C
87 ldr r0, REG_FUNC_MUX_CTRL_D
88 ldr r1, VAL_FUNC_MUX_CTRL_D
90 ldr r0, REG_VOLTAGE_CTRL_0
91 ldr r1, VAL_VOLTAGE_CTRL_0
93 ldr r0, REG_TEST_DBG_CTRL_0
94 ldr r1, VAL_TEST_DBG_CTRL_0
96 ldr r0, REG_MOD_CONF_CTRL_0
97 ldr r1, VAL_MOD_CONF_CTRL_0
100 /* Move to 1510 mode */
101 ldr r0, REG_COMP_MODE_CTRL_0
102 ldr r1, VAL_COMP_MODE_CTRL_0
105 /* Set up Traffic Ctlr*/
106 ldr r0, REG_TC_IMIF_PRIO
109 ldr r0, REG_TC_EMIFS_PRIO
111 ldr r0, REG_TC_EMIFF_PRIO
114 ldr r0, REG_TC_EMIFS_CONFIG
116 bic r1, r1, #0x08 /* clear the global power-down enable PDE bit */
117 bic r1, r1, #0x01 /* write protect flash by clearing the WP bit */
118 str r1, [r0] /* EMIFS GlB Configuration. (value 0x12 most likely) */
120 /* Setup some clock domains */
121 ldr r1, =OMAP1510_CLKS
122 ldr r0, REG_ARM_IDLECT2
123 strh r1, [r0] /* CLKM, Clock domain control. */
125 mov r1, #0x01 /* PER_EN bit */
126 ldr r0, REG_ARM_RSTCT2
127 strh r1, [r0] /* CLKM; Peripheral reset. */
129 /* Set CLKM to Sync-Scalable */
130 /* I supposidly need to enable the dsp clock before switching */
132 ldr r0, REG_ARM_SYSST
136 subs r0, r0, #0x1 /* wait for any bubbles to finish */
139 ldr r1, VAL_ARM_CKCTL /* use 12Mhz ref, PER must be <= 50Mhz so /2 */
140 ldr r0, REG_ARM_CKCTL
144 ldr r1, VAL_DPLL1_CTL
145 ldr r0, REG_DPLL1_CTL
147 ands r1, r1, #0x10 /* Check if PLL is enabled. */
148 beq lock_end /* Do not look for lock if BYPASS selected */
151 ands r1, r1, #0x01 /* Check the LOCK bit. */
152 beq 2b /* ...loop until bit goes hi. */
155 /* Set memory timings corresponding to the new clock speed */
157 /* Check execution location to determine current execution location
158 * and branch to appropriate initialization code.
160 mov r0, #0x10000000 /* Load physical SDRAM base. */
161 mov r1, pc /* Get current execution location. */
162 /* Zero all but top 6 bits of PC, as they alone detect whether an
163 * address is in the range 0x1000:0000-0x13ff:ffff, the 64M sized
164 * valid range for SDRAM on the OMAP 1510/5910.
166 and r1, r1, #0xfc000000
167 cmp r1, r0 /* Compare. */
168 beq skip_sdram /* Skip over EMIF-fast initialization
169 * if running from SDRAM.
173 * Delay for SDRAM initialization.
175 mov r3, #0x1800 /* value should be checked */
177 subs r3, r3, #0x1 /* Decrement count */
181 * Set SDRAM control values. Disable refresh before MRS command.
183 ldr r0, VAL_TC_EMIFF_SDRAM_CONFIG /* get good value */
184 bic r3, r0, #0xC /* (BIT3|BIT2) ulConfig with auto-refresh disabled. */
185 orr r3, r3, #0x8000000 /* (BIT27) Disable CLK when Power down or Self-Refresh */
186 orr r3, r3, #0x4000000 /* BIT26 Power Down Enable */
187 ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
188 str r3, [r2] /* Store the passed value with AR disabled. */
190 ldr r1, VAL_TC_EMIFF_MRS /* get MRS value */
191 ldr r2, REG_TC_EMIFF_MRS /* Point to MRS register. */
192 str r1, [r2] /* Store the passed value.*/
194 ldr r2, REG_TC_EMIFF_SDRAM_CONFIG /* Point to configuration register. */
195 str r0, [r2] /* Store the passed value. */
198 * Delay for SDRAM initialization.
202 subs r3, r3, #1 /* Decrement count. */
208 ldr r1, VAL_TC_EMIFS_CS0_CONFIG
209 ldr r0, REG_TC_EMIFS_CS0_CONFIG
210 str r1, [r0] /* Chip Select 0 */
211 ldr r1, VAL_TC_EMIFS_CS1_CONFIG
212 ldr r0, REG_TC_EMIFS_CS1_CONFIG
213 str r1, [r0] /* Chip Select 1 */
214 ldr r1, VAL_TC_EMIFS_CS2_CONFIG
215 ldr r0, REG_TC_EMIFS_CS2_CONFIG
216 str r1, [r0] /* Chip Select 2 */
217 ldr r1, VAL_TC_EMIFS_CS3_CONFIG
218 ldr r0, REG_TC_EMIFS_CS3_CONFIG
219 str r1, [r0] /* Chip Select 3 */
221 /* Next, Enable the RS232 Line Drivers in the FPGA. */
222 /* Also, power on the audio CODEC's amplifier here, */
223 /* which will make a noise on the audio output. */
224 /* This is done here instead of in the kernel so there */
225 /* isn't a loud popping noise at the start of each */
227 /* Also, disable the CODEC's clocks. */
228 /* omap1510-HelenP1 [specific] */
230 ldr r0, REG_FPGA_POWER
232 ldr r2, REG_FPGA_DIP_SWITCH
235 movne r1, #0x62 /* Enable the RS232 Line Drivers in the EPLD */
237 ldr r0, REG_FPGA_AUDIO
238 mov r1, #0x0 /* Disable sound driver (CODEC clocks) */
241 /* back to arch calling code */
244 /* the literal pools origin */
247 /* OMAP configuration registers */
248 REG_FUNC_MUX_CTRL_0: /* 32 bits */
250 REG_FUNC_MUX_CTRL_1: /* 32 bits */
252 REG_FUNC_MUX_CTRL_2: /* 32 bits */
254 REG_COMP_MODE_CTRL_0: /* 32 bits */
256 REG_FUNC_MUX_CTRL_3: /* 32 bits */
258 REG_FUNC_MUX_CTRL_4: /* 32 bits */
260 REG_FUNC_MUX_CTRL_5: /* 32 bits */
262 REG_FUNC_MUX_CTRL_6: /* 32 bits */
264 REG_FUNC_MUX_CTRL_7: /* 32 bits */
266 REG_FUNC_MUX_CTRL_8: /* 32 bits */
268 REG_FUNC_MUX_CTRL_9: /* 32 bits */
270 REG_FUNC_MUX_CTRL_A: /* 32 bits */
272 REG_FUNC_MUX_CTRL_B: /* 32 bits */
274 REG_FUNC_MUX_CTRL_C: /* 32 bits */
276 REG_FUNC_MUX_CTRL_D: /* 32 bits */
278 REG_PULL_DWN_CTRL_0: /* 32 bits */
280 REG_PULL_DWN_CTRL_1: /* 32 bits */
282 REG_PULL_DWN_CTRL_2: /* 32 bits */
284 REG_PULL_DWN_CTRL_3: /* 32 bits */
286 REG_VOLTAGE_CTRL_0: /* 32 bits */
288 REG_TEST_DBG_CTRL_0: /* 32 bits */
290 REG_MOD_CONF_CTRL_0: /* 32 bits */
292 REG_TC_IMIF_PRIO: /* 32 bits */
294 REG_TC_EMIFS_PRIO: /* 32 bits */
296 REG_TC_EMIFF_PRIO: /* 32 bits */
298 REG_TC_EMIFS_CONFIG: /* 32 bits */
300 REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
302 REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
304 REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
306 REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
308 REG_TC_EMIFF_SDRAM_CONFIG: /* 32 bits */
310 REG_TC_EMIFF_MRS: /* 32 bits */
312 /* MPU clock/reset/power mode control registers */
313 REG_ARM_CKCTL: /* 16 bits */
315 REG_ARM_IDLECT2: /* 16 bits */
317 REG_ARM_RSTCT2: /* 16 bits */
319 REG_ARM_SYSST: /* 16 bits */
321 /* DPLL control registers */
322 REG_DPLL1_CTL: /* 16 bits */
324 /* identification code register */
325 REG_IDCODE: /* 32 bits */
328 /* Innovator specific */
329 REG_FPGA_LED_DIGIT: /* 8 bits (not used on Innovator) */
331 REG_FPGA_POWER: /* 8 bits */
333 REG_FPGA_AUDIO: /* 8 bits (not used on Innovator) */
335 REG_FPGA_DIP_SWITCH: /* 8 bits (not used on Innovator) */
338 VAL_COMP_MODE_CTRL_0:
371 /* See Errata 4.13, This works around a SRAM bug, for chips below ES2.5 .
372 * This slows down internal SRAM accesses.
381 VAL_TC_EMIFS_CS1_CONFIG_PRELIM:
383 VAL_TC_EMIFS_CS2_CONFIG_PRELIM:
385 VAL_TC_EMIFS_CS0_CONFIG:
387 VAL_TC_EMIFS_CS1_CONFIG:
389 VAL_TC_EMIFS_CS2_CONFIG:
391 VAL_TC_EMIFS_CS3_CONFIG:
393 VAL_TC_EMIFF_SDRAM_CONFIG: