git.sur5r.net Git - u-boot/blob - board/omap2420h4/omap2420h4.c

   1 /*
   2  * (C) Copyright 2004
   3  * Texas Instruments, <www.ti.com>
   4  * Richard Woodruff <r-woodruff2@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24 #include <common.h>
  25 #include <asm/arch/omap2420.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/bits.h>
  28 #include <asm/arch/mux.h>
  29 #include <asm/arch/sys_proto.h>
  30 #include <asm/arch/sys_info.h>
  31 #include <asm/arch/mem.h>
  32 #include <i2c.h>
  33 #include <asm/mach-types.h>
  34
  35 static void wait_for_command_complete(unsigned int wd_base);
  36
  37 /*******************************************************
  38  * Routine: delay
  39  * Description: spinning delay to use before udelay works
  40  ******************************************************/
  41 static inline void delay (unsigned long loops)
  42 {
  43         __asm__ volatile ("1:\n"
  44                                           "subs %0, %1, #1\n"
  45                                           "bne 1b":"=r" (loops):"0" (loops));
  46 }
  47
  48 /*****************************************
  49  * Routine: board_init
  50  * Description: Early hardware init.
  51  *****************************************/
  52 int board_init (void)
  53 {
  54         DECLARE_GLOBAL_DATA_PTR;
  55 #ifndef CONFIG_PARTIAL_SRAM
  56         s_init(0x0);  /* full sram build, never skip clock and sdrc, no point */
  57 #else
  58         gpmc_init();
  59 #endif
  60         gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4;             /* board id for linux */
  61         gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100);     /* adress of boot parameters */
  62
  63         return 0;
  64 }
  65
  66 /**********************************************************
  67  * Routine: s_init
  68  * Description: Does early system init of muxing and clocks.
  69  * - Called at time when only stack is available.
  70  **********************************************************/
  71 void s_init(int skip)
  72 {
  73         watchdog_init();
  74         set_muxconf_regs();
  75         delay(100);
  76
  77         if (!skip)
  78                 prcm_init();
  79
  80         peripheral_enable();
  81         icache_enable();
  82 #ifndef CONFIG_APTIX
  83         if (!skip)
  84                 memif_init();
  85 #endif
  86 }
  87
  88 /*******************************************************
  89  * Routine: misc_init_r
  90  * Description: Init ethernet (done here so udelay works)
  91  ********************************************************/
  92 int misc_init_r (void)
  93 {
  94         ether_init(); /* better done here so timers are init'ed */
  95         return(0);
  96 }
  97
  98 /****************************************
  99  * Routine: watchdog_init
 100  * Description: Shut down watch dogs
 101  *****************************************/
 102 void watchdog_init(void)
 103 {
 104         int mode;
 105 #define GP (BIT8|BIT9)
 106
 107         /* There are 4 watch dogs.  1 secure, and 3 general purpose.
 108          * I would expect that the ROM takes care of the secure one,
 109          * but we will try also.  Of the 3 GP ones, 1 can reset us
 110          * directly, the other 2 only generate MPU interrupts.
 111          */
 112         mode = (__raw_readl(CONTROL_STATUS) & (BIT8|BIT9));
 113         if (mode == GP) {
 114                 __raw_writel(WD_UNLOCK1 ,WD1_BASE+WSPR);
 115                 wait_for_command_complete(WD1_BASE);
 116                 __raw_writel(WD_UNLOCK2 ,WD1_BASE+WSPR);
 117         }
 118         __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR);
 119         wait_for_command_complete(WD2_BASE);
 120         __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR);
 121
 122 #if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/
 123         __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR);
 124         wait_for_command_complete(WD3_BASE);
 125         __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR);
 126
 127         __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR);
 128         wait_for_command_complete(WD4_BASE);
 129         __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR);
 130 #endif
 131 }
 132
 133 /******************************************************
 134  * Routine: wait_for_command_complete
 135  * Description: Wait for posting to finish on watchdog
 136  ******************************************************/
 137 static void wait_for_command_complete(unsigned int wd_base)
 138 {
 139         int pending = 1;
 140         do {
 141                 pending = __raw_readl(wd_base+WWPS);
 142         } while (pending);
 143 }
 144
 145 /*******************************************************************
 146  * Routine:ether_init
 147  * Description: take the Ethernet controller out of reset and wait
 148  *                 for the EEPROM load to complete.
 149  ******************************************************************/
 150 void ether_init (void)
 151 {
 152 #ifdef CONFIG_DRIVER_LAN91C96
 153         int cnt = 20;
 154
 155         __raw_writew(0x0, LAN_RESET_REGISTER);
 156         do {
 157                 __raw_writew(0x1, LAN_RESET_REGISTER);
 158                 udelay (100);
 159                 if (cnt == 0)
 160                         goto h4reset_err_out;
 161                 --cnt;
 162         } while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
 163
 164         cnt = 20;
 165
 166         do {
 167                 __raw_writew(0x0, LAN_RESET_REGISTER);
 168                 udelay (100);
 169                 if (cnt == 0)
 170                         goto h4reset_err_out;
 171                 --cnt;
 172         } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
 173         udelay (1000);
 174
 175         *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01;
 176         udelay (1000);
 177
 178         h4reset_err_out:
 179         return;
 180 #endif
 181 }
 182
 183 /**********************************************
 184  * Routine: dram_init
 185  * Description: sets uboots idea of sdram size
 186  **********************************************/
 187 int dram_init (void)
 188 {
 189         DECLARE_GLOBAL_DATA_PTR;
 190         unsigned int size0=0,size1=0;
 191         u32 mtype, btype;
 192 #define NOT_EARLY 0
 193
 194         i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
 195
 196         btype = get_board_type();
 197         mtype = get_mem_type();
 198
 199         display_board_info(btype);
 200         if (btype == BOARD_H4_MENELAUS)
 201                 update_mux(btype,mtype);
 202
 203         if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
 204                 do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
 205                 size0 = size1 = SZ_32M;
 206         } else
 207                 size0 = SZ_64M;
 208
 209         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 210         gd->bd->bi_dram[0].size = size0;
 211         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 212         gd->bd->bi_dram[1].size = size1;
 213
 214         return 0;
 215 }
 216
 217 /**********************************************************
 218  * Routine: set_muxconf_regs
 219  * Description: Setting up the configuration Mux registers
 220  *              specific to the hardware
 221  *********************************************************/
 222 void set_muxconf_regs (void)
 223 {
 224         muxSetupSDRC();
 225         muxSetupGPMC();
 226         muxSetupUsb0();
 227         muxSetupUart3();
 228         muxSetupI2C1();
 229         muxSetupUART1();
 230         muxSetupLCD();
 231         muxSetupCamera();
 232         muxSetupMMCSD();
 233         muxSetupTouchScreen();
 234         muxSetupHDQ();
 235 }
 236
 237 /*****************************************************************
 238  * Routine: peripheral_enable
 239  * Description: Enable the clks & power for perifs (GPT2, UART1,...)
 240  ******************************************************************/
 241 void peripheral_enable(void)
 242 {
 243         unsigned int v, if_clks=0, func_clks=0;
 244
 245         /* Enable GP2 timer.*/
 246         if_clks |= BIT4;
 247         func_clks |= BIT4;
 248         v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */
 249         __raw_writel(v, CM_CLKSEL2_CORE);
 250         __raw_writel(0x1, CM_CLKSEL_WKUP);
 251
 252 #ifdef CFG_NS16550
 253         /* Enable UART1 clock */
 254         func_clks |= BIT21;
 255         if_clks |= BIT21;
 256 #endif
 257         v = __raw_readl(CM_ICLKEN1_CORE) | if_clks;     /* Interface clocks on */
 258         __raw_writel(v,CM_ICLKEN1_CORE );
 259         v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
 260         __raw_writel(v, CM_FCLKEN1_CORE);
 261         delay(1000);
 262
 263 #ifndef KERNEL_UPDATED
 264         {
 265 #define V1 0xffffffff
 266 #define V2 0x00000007
 267
 268                 __raw_writel(V1, CM_FCLKEN1_CORE);
 269                 __raw_writel(V2, CM_FCLKEN2_CORE);
 270                 __raw_writel(V1, CM_ICLKEN1_CORE);
 271                 __raw_writel(V1, CM_ICLKEN2_CORE);
 272         }
 273 #endif
 274 }
 275
 276 /****************************************
 277  * Routine: muxSetupUsb0   (ostboot)
 278  * Description: Setup usb muxing
 279  *****************************************/
 280 void muxSetupUsb0(void)
 281 {
 282         volatile uint8   *MuxConfigReg;
 283         volatile uint32  *otgCtrlReg;
 284
 285         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
 286         *MuxConfigReg &= (uint8)(~0x1F);
 287
 288         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
 289         *MuxConfigReg &= (uint8)(~0x1F);
 290
 291         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
 292         *MuxConfigReg &= (uint8)(~0x1F);
 293
 294         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
 295         *MuxConfigReg &= (uint8)(~0x1F);
 296
 297         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
 298         *MuxConfigReg &= (uint8)(~0x1F);
 299
 300         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
 301         *MuxConfigReg &= (uint8)(~0x1F);
 302
 303         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
 304         *MuxConfigReg &= (uint8)(~0x1F);
 305
 306         /* setup for USB VBus detection */
 307         otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL;
 308         *otgCtrlReg |= 0x00040000; /* bit 18 */
 309 }
 310
 311 /****************************************
 312  * Routine: muxSetupUart3   (ostboot)
 313  * Description: Setup uart3 muxing
 314  *****************************************/
 315 void muxSetupUart3(void)
 316 {
 317         volatile uint8 *MuxConfigReg;
 318
 319         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX;
 320         *MuxConfigReg &= (uint8)(~0x1F);
 321
 322         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX;
 323         *MuxConfigReg &= (uint8)(~0x1F);
 324 }
 325
 326 /****************************************
 327  * Routine: muxSetupI2C1   (ostboot)
 328  * Description: Setup i2c muxing
 329  *****************************************/
 330 void muxSetupI2C1(void)
 331 {
 332         volatile unsigned char  *MuxConfigReg;
 333
 334         /* I2C1 Clock pin configuration, PIN = M19 */
 335         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
 336         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 337
 338         /* I2C1 Data pin configuration, PIN = L15 */
 339         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
 340         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 341
 342         /* Pull-up required on data line */
 343         /* external pull-up already present. */
 344         /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */
 345 }
 346
 347 /****************************************
 348  * Routine: muxSetupUART1  (ostboot)
 349  * Description: Set up uart1 muxing
 350  *****************************************/
 351 void muxSetupUART1(void)
 352 {
 353         volatile unsigned char  *MuxConfigReg;
 354
 355         /* UART1_CTS pin configuration, PIN = D21 */
 356         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
 357         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 358
 359         /* UART1_RTS pin configuration, PIN = H21 */
 360         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
 361         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 362
 363         /* UART1_TX pin configuration, PIN = L20 */
 364         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
 365         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 366
 367         /* UART1_RX pin configuration, PIN = T21 */
 368         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
 369         *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
 370 }
 371
 372 /****************************************
 373  * Routine: muxSetupLCD   (ostboot)
 374  * Description: Setup lcd muxing
 375  *****************************************/
 376 void muxSetupLCD(void)
 377 {
 378         volatile unsigned char  *MuxConfigReg;
 379
 380         /* LCD_D0 pin configuration, PIN = Y7  */
 381         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
 382         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 383
 384         /* LCD_D1 pin configuration, PIN = P10 */
 385         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
 386         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 387
 388         /* LCD_D2 pin configuration, PIN = V8  */
 389         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
 390         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 391
 392         /* LCD_D3 pin configuration, PIN = Y8  */
 393         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
 394         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 395
 396         /* LCD_D4 pin configuration, PIN = W8  */
 397         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
 398         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 399
 400         /* LCD_D5 pin configuration, PIN = R10 */
 401         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
 402         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 403
 404         /* LCD_D6 pin configuration, PIN = Y9  */
 405         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
 406         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 407
 408         /* LCD_D7 pin configuration, PIN = V9  */
 409         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
 410         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 411
 412         /* LCD_D8 pin configuration, PIN = W9  */
 413         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
 414         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 415
 416         /* LCD_D9 pin configuration, PIN = P11 */
 417         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
 418         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 419
 420         /* LCD_D10 pin configuration, PIN = V10 */
 421         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
 422         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 423
 424         /* LCD_D11 pin configuration, PIN = Y10 */
 425         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
 426         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 427
 428         /* LCD_D12 pin configuration, PIN = W10 */
 429         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
 430         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 431
 432         /* LCD_D13 pin configuration, PIN = R11 */
 433         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
 434         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 435
 436         /* LCD_D14 pin configuration, PIN = V11 */
 437         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
 438         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 439
 440         /* LCD_D15 pin configuration, PIN = W11 */
 441         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
 442         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 443
 444         /* LCD_D16 pin configuration, PIN = P12 */
 445         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
 446         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 447
 448         /* LCD_D17 pin configuration, PIN = R12 */
 449         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
 450         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 451
 452         /* LCD_PCLK pin configuration,   PIN = W6   */
 453         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
 454         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 455
 456         /* LCD_VSYNC pin configuration,  PIN = V7  */
 457         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
 458         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 459
 460         /* LCD_HSYNC pin configuration,  PIN = Y6  */
 461         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
 462         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 463
 464         /* LCD_ACBIAS pin configuration, PIN = W7 */
 465         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
 466         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 467 }
 468
 469 /****************************************
 470  * Routine: muxSetupCamera  (ostboot)
 471  * Description: Setup camera muxing
 472  *****************************************/
 473 void muxSetupCamera(void)
 474 {
 475         volatile unsigned char  *MuxConfigReg;
 476
 477         /* CAMERA_RSTZ  pin configuration, PIN = Y16 */
 478         /* CAM_RST is connected through the I2C IO expander.*/
 479         /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
 480         /* *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled   */
 481
 482         /* CAMERA_XCLK  pin configuration, PIN = U3 */
 483         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
 484         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 485
 486         /* CAMERA_LCLK  pin configuration, PIN = V5 */
 487         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
 488         *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 489
 490         /* CAMERA_VSYNC pin configuration, PIN = U2 */
 491         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
 492                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 493
 494         /* CAMERA_HSYNC pin configuration, PIN = T3 */
 495         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
 496                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 497
 498         /* CAMERA_DAT0 pin configuration, PIN = T4 */
 499         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
 500                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 501
 502         /* CAMERA_DAT1 pin configuration, PIN = V2 */
 503         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
 504                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 505
 506         /* CAMERA_DAT2 pin configuration, PIN = V3 */
 507         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
 508                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 509
 510         /* CAMERA_DAT3 pin configuration, PIN = U4 */
 511         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
 512                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 513
 514         /* CAMERA_DAT4 pin configuration, PIN = W2 */
 515         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
 516                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 517
 518         /* CAMERA_DAT5 pin configuration, PIN = V4 */
 519         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
 520                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 521
 522         /* CAMERA_DAT6 pin configuration, PIN = W3 */
 523         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
 524                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 525
 526         /* CAMERA_DAT7 pin configuration, PIN = Y2 */
 527         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
 528                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 529
 530         /* CAMERA_DAT8 pin configuration, PIN = Y4 */
 531         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
 532                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 533
 534         /* CAMERA_DAT9 pin configuration, PIN = V6 */
 535         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
 536                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 537 }
 538
 539 /****************************************
 540  * Routine: muxSetupMMCSD (ostboot)
 541  * Description: set up MMC muxing
 542  *****************************************/
 543 void muxSetupMMCSD(void)
 544 {
 545         volatile unsigned char  *MuxConfigReg;
 546
 547         /* SDMMC_CLKI pin configuration,  PIN = H15 */
 548         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
 549                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 550
 551         /* SDMMC_CLKO pin configuration,  PIN = G19 */
 552         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
 553                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 554
 555         /* SDMMC_CMD pin configuration,   PIN = H18 */
 556         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
 557                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 558         // External pull-ups are present.
 559         // *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
 560
 561         /* SDMMC_DAT0 pin configuration,  PIN = F20 */
 562         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
 563                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 564         // External pull-ups are present.
 565         // *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
 566
 567         /* SDMMC_DAT1 pin configuration,  PIN = H14 */
 568         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
 569                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 570         // External pull-ups are present.
 571         // *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
 572
 573         /* SDMMC_DAT2 pin configuration,  PIN = E19 */
 574         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
 575                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 576         // External pull-ups are present.
 577         // *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
 578
 579         /* SDMMC_DAT3 pin configuration,  PIN = D19 */
 580         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
 581                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 582         // External pull-ups are present.
 583         // *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
 584
 585         /* SDMMC_DDIR0 pin configuration, PIN = F19 */
 586         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
 587                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 588
 589         /* SDMMC_DDIR1 pin configuration, PIN = E20 */
 590         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
 591                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 592
 593         /* SDMMC_DDIR2 pin configuration, PIN = F18 */
 594         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
 595                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 596
 597         /* SDMMC_DDIR3 pin configuration, PIN = E18 */
 598         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
 599                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 600
 601         /* SDMMC_CDIR pin configuration,  PIN = G18 */
 602         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
 603                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 604
 605         /* MMC_CD pin configuration,      PIN = B3  ---2420IP ONLY---*/
 606         /* MMC_CD for 2422IP=K1 */
 607         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
 608                                    *MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
 609
 610         /* MMC_WP pin configuration,      PIN = B4  */
 611         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
 612                                    *MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
 613 }
 614
 615 /******************************************
 616  * Routine: muxSetupTouchScreen (ostboot)
 617  * Description:  Set up touch screen muxing
 618  *******************************************/
 619 void muxSetupTouchScreen(void)
 620 {
 621         volatile unsigned char  *MuxConfigReg;
 622
 623         /* SPI1_CLK pin configuration,  PIN = U18 */
 624         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
 625                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 626
 627         /* SPI1_MOSI pin configuration, PIN = V20 */
 628         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
 629                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 630
 631         /* SPI1_MISO pin configuration, PIN = T18 */
 632         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
 633                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 634
 635         /* SPI1_nCS0 pin configuration, PIN = U19 */
 636         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
 637                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 638
 639         /* PEN_IRQ pin configuration,   PIN = P20 */
 640         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
 641                                    *MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
 642 }
 643
 644 /****************************************
 645  * Routine: muxSetupHDQ (ostboot)
 646  * Description: setup 1wire mux
 647  *****************************************/
 648 void muxSetupHDQ(void)
 649 {
 650         volatile unsigned char  *MuxConfigReg;
 651
 652         /* HDQ_SIO pin configuration,  PIN = N18 */
 653         MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
 654                                    *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
 655 }
 656
 657 /***************************************************************
 658  * Routine: muxSetupGPMC (ostboot)
 659  * Description: Configures balls which cam up in protected mode
 660  ***************************************************************/
 661 void muxSetupGPMC(void)
 662 {
 663         volatile uint8 *MuxConfigReg;
 664         volatile unsigned int *MCR = 0x4800008C;
 665
 666         /* gpmc_io_dir */
 667         *MCR = 0x19000000;
 668
 669         /* NOR FLASH CS0 */
 670         /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3       Pull/up - N/A */
 671         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3,
 672                                    *MuxConfigReg = 0x00 ;
 673
 674         /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3     Pull/up - N/A */
 675         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3,
 676                                    *MuxConfigReg = 0x01 ;
 677
 678         /* MPDB(Multi Port Debug Port) CS1 */
 679         /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1      Pull/up - N/A */
 680         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1,
 681                                    *MuxConfigReg = 0x00 ;
 682
 683         /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2      Pull/up - N/A */
 684         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2,
 685                                    *MuxConfigReg = 0x00 ;
 686
 687
 688 }
 689
 690 /****************************************************************
 691  * Routine: muxSetupSDRC  (ostboot)
 692  * Description: Configures balls which come up in protected mode
 693  ****************************************************************/
 694 void muxSetupSDRC(void)
 695 {
 696         volatile uint8 *MuxConfigReg;
 697
 698         /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1     Pull/up - N/A */
 699         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1,
 700                                    *MuxConfigReg = 0x00 ;
 701
 702         /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2      Pull/up - N/A */
 703         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2,
 704                                    *MuxConfigReg = 0x00 ;
 705
 706         /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3     Pull/up - N/A */
 707         MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3,
 708                                    *MuxConfigReg = 0x00;
 709
 710         if (get_cpu_type() == CPU_2422) {
 711                 MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0,
 712                                            *MuxConfigReg = 0x1b;
 713         }
 714 }
 715
 716 /*****************************************************************************
 717  * Routine: update_mux()
 718  * Description: Update balls which are different beween boards.  All should be
 719  *              updated to match functionaly.  However, I'm only updating ones
 720  *              which I'll be using for now.  When power comes into play they
 721  *              all need updating.
 722  *****************************************************************************/
 723 void update_mux(u32 btype,u32 mtype)
 724 {
 725         u32 cpu, base = OMAP2420_CTRL_BASE;
 726         cpu = get_cpu_type();
 727
 728         if (btype == BOARD_H4_MENELAUS) {
 729                 if (cpu == CPU_2420) {
 730                         /* PIN = B3,  GPIO.0->KBR5,      mode 3,  (pun?),-DO-*/
 731                         __raw_writeb(0x3, base+0x30);
 732                         /* PIN = B13, GPIO.38->KBC6,     mode 3,  (pun?)-DO-*/
 733                         __raw_writeb(0x3, base+0xa3);
 734                         /* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
 735                         /* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
 736                         /* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
 737                         /* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
 738                         /* PIN = M1 (HSUSBOTG) */
 739                         /* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
 740                         __raw_writeb(0x3, base+0x9d);
 741                         /* PIN = U32, (WLAN_CLKREQ) */
 742                         /* PIN = Y11, WLAN */
 743                         /* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
 744                         __raw_writeb(0x3, base+0xe7);
 745                         /* PIN = AA8, mDOC */
 746                         /* PIN = AA10, BT */
 747                         /* PIN = AA13, WLAN */
 748                         /* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
 749                         __raw_writeb(0x3, base+0x10e);
 750                         /* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
 751                         __raw_writeb(0x3, base+0x110);
 752                         /* PIN = J15 HHUSB */
 753                         /* PIN = H19 HSUSB */
 754                         /* PIN = W13, P13, R13, W16 ... */
 755                         /* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
 756                         __raw_writeb(0x3, base+0xde);
 757                         /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
 758                         __raw_writeb(0x0, base+0x12c);
 759                         /* PIN = AA17->sys_clkreq        mode 0   -DO- */
 760                         __raw_writeb(0x0, base+0x136);
 761                 } else if (cpu == CPU_2422) {
 762                         /* PIN = B3,  GPIO.0->nc,        mode 3,  set above (pun?)*/
 763                         /* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
 764                         /* PIN = F1, GPIO.25->HSUSBxx    mode 3,  (for external HS USB)*/
 765                         /* PIN = H1, GPIO.26->HSUSBxx    mode 3,  (for external HS USB)*/
 766                         /* PIN = K1, GPMC_ncs6           mode 0,  (on board nand access)*/
 767                         __raw_writeb(0x0, base+0x92);
 768                         /* PIN = L2, GPMC_ncs67          mode 0,  (for external HS USB)*/
 769                         /* PIN = M1 (HSUSBOTG) */
 770                         /* PIN = P1, GPIO.35->MEN_POK    mode 3,  (menelaus powerok)-DO-*/
 771                         __raw_writeb(0x3, base+0x10c);
 772                         /* PIN = U32, (WLAN_CLKREQ) */
 773                         /* PIN = AA4, GPIO.15->KBC2,     mode 3,  -DO- */
 774                         __raw_writeb(0x3, base+0x30);
 775                         /* PIN = AA8, mDOC */
 776                         /* PIN = AA10, BT */
 777                         /* PIN = AA12, WLAN */
 778                         /* PIN = M18 GPIO.96->MMC2_WP    mode 3   -DO- */
 779                         __raw_writeb(0x3, base+0x10e);
 780                         /* PIN = N19 GPIO.98->WLAN_INT   mode 3   -DO- */
 781                         __raw_writeb(0x3, base+0x110);
 782                         /* PIN = J15 HHUSB */
 783                         /* PIN = H19 HSUSB */
 784                         /* PIN = W13, P13, R13, W16 ... */
 785                         /* PIN = V12 GPIO.25->I2C_CAMEN  mode 3   -DO- */
 786                         __raw_writeb(0x3, base+0xde);
 787                         /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */
 788                         __raw_writeb(0x0, base+0x12c);
 789                         /* PIN = AA17->sys_clkreq        mode 0   -DO- */
 790                         __raw_writeb(0x0, base+0x136);
 791                 }
 792
 793         } else if (btype == BOARD_H4_SDP) {
 794                 if (cpu == CPU_2420) {
 795                         /* PIN = B3,  GPIO.0->nc         mode 3,  set above (pun?)*/
 796                         /* PIN = B13, GPIO.cke1->nc,     mode 0,  set above, (pun?)*/
 797                         /* Pin = Y11 VLNQ */
 798                         /* Pin = AA4 VLNQ */
 799                         /* Pin = AA6 VLNQ */
 800                         /* Pin = AA8 VLNQ */
 801                         /* Pin = AA10 VLNQ */
 802                         /* Pin = AA12 VLNQ */
 803                         /* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
 804                         __raw_writeb(0x3, base+0x10e);
 805                         /* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
 806                         __raw_writeb(0x3, base+0x110);
 807                         /* PIN = J15 MDOC_nDMAREQ */
 808                         /* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
 809                         __raw_writeb(0x3, base+0x114);
 810                         /* PIN = W13, V12, P13, R13, W19, W16 ... */
 811                         /* PIN = AA17 sys_clkreq->bt_clk_req  mode 0  */
 812                 } else if (cpu == CPU_2422) {
 813                         /* PIN = B3,  GPIO.0->MMC_CD,    mode 3,  set above */
 814                         /* PIN = B13, GPIO.38->wlan_int, mode 3,  (pun?)*/
 815                         /* Pin = Y11 VLNQ */
 816                         /* Pin = AA4 VLNQ */
 817                         /* Pin = AA6 VLNQ */
 818                         /* Pin = AA8 VLNQ */
 819                         /* Pin = AA10 VLNQ */
 820                         /* Pin = AA12 VLNQ */
 821                         /* PIN = M18 GPIO.96->KBR5       mode 3   -DO- */
 822                         __raw_writeb(0x3, base+0x10e);
 823                         /* PIN = N19 GPIO.98->KBC6       mode 3   -DO- */
 824                         __raw_writeb(0x3, base+0x110);
 825                         /* PIN = J15 MDOC_nDMAREQ */
 826                         /* PIN = H19 GPIO.100->KBC2      mode 3   -DO- */
 827                         __raw_writeb(0x3, base+0x114);
 828                         /* PIN = W13, V12, P13, R13, W19, W16 ... */
 829                         /* PIN = AA17 sys_clkreq->bt_clk_req  mode 0 */
 830                 }
 831         }
 832 }
 833
 834