2 * (C) Copyright 2004-2008
3 * Texas Instruments, <www.ti.com>
6 * Manikandan Pillai <mani.pillai@ti.com>
8 * Derived from Beagle Board and 3430 SDP code by
9 * Richard Woodruff <r-woodruff2@ti.com>
10 * Syed Mohammed Khasim <khasim@ti.com>
12 * See file CREDITS for list of people who contributed to this
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #include <asm/arch/mem.h>
33 #include <asm/arch/mux.h>
34 #include <asm/arch/sys_proto.h>
36 #include <asm/mach-types.h>
39 /******************************************************************************
41 * Description: Early hardware init.
42 *****************************************************************************/
45 DECLARE_GLOBAL_DATA_PTR;
47 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
48 /* board id for Linux */
49 gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
51 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
56 /******************************************************************************
57 * Routine: misc_init_r
58 * Description: Init ethernet (done here so udelay works)
59 *****************************************************************************/
63 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
64 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
67 #if defined(CONFIG_CMD_NET)
76 /******************************************************************************
77 * Routine: set_muxconf_regs
78 * Description: Setting up the configuration Mux registers specific to the
79 * hardware. Many pins need to be moved from protect to primary
81 *****************************************************************************/
82 void set_muxconf_regs(void)
87 /******************************************************************************
88 * Routine: setup_net_chip
89 * Description: Setting up the configuration GPMC registers specific to the
91 *****************************************************************************/
92 static void setup_net_chip(void)
94 gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
95 gpmc_csx_t *gpmc_cs6_base = (gpmc_csx_t *)GPMC_CONFIG_CS6_BASE;
96 ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
98 /* Configure GPMC registers */
99 writel(NET_GPMC_CONFIG1, &gpmc_cs6_base->config1);
100 writel(NET_GPMC_CONFIG2, &gpmc_cs6_base->config2);
101 writel(NET_GPMC_CONFIG3, &gpmc_cs6_base->config3);
102 writel(NET_GPMC_CONFIG4, &gpmc_cs6_base->config4);
103 writel(NET_GPMC_CONFIG5, &gpmc_cs6_base->config5);
104 writel(NET_GPMC_CONFIG6, &gpmc_cs6_base->config6);
105 writel(NET_GPMC_CONFIG7, &gpmc_cs6_base->config7);
107 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
108 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
109 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
110 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
111 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
112 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
113 &ctrl_base->gpmc_nadv_ale);
115 /* Make GPIO 64 as output pin */
116 writel(readl(&gpio3_base->oe) & ~(GPIO0), &gpio3_base->oe);
118 /* Now send a pulse on the GPIO pin */
119 writel(GPIO0, &gpio3_base->setdataout);
121 writel(GPIO0, &gpio3_base->cleardataout);
123 writel(GPIO0, &gpio3_base->setdataout);