2 * Board specific setup info
5 * Texas Instruments, <www.ti.com>
6 * Kshitij Gupta <Kshitij@ti.com>
8 * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
10 * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #if defined(CONFIG_OMAP1610)
34 #include <./configs/omap1510.h>
39 .word TEXT_BASE /* sdram load addr from config.mk */
45 /*------------------------------------------------------*
46 *mask all IRQs by setting all bits in the INTMR default*
47 *------------------------------------------------------*/
54 /*------------------------------------------------------*
55 * Set up ARM CLM registers (IDLECT1) *
56 *------------------------------------------------------*/
57 ldr r0, REG_ARM_IDLECT1
58 ldr r1, VAL_ARM_IDLECT1
61 /*------------------------------------------------------*
62 * Set up ARM CLM registers (IDLECT2) *
63 *------------------------------------------------------*/
64 ldr r0, REG_ARM_IDLECT2
65 ldr r1, VAL_ARM_IDLECT2
68 /*------------------------------------------------------*
69 * Set up ARM CLM registers (IDLECT3) *
70 *------------------------------------------------------*/
71 ldr r0, REG_ARM_IDLECT3
72 ldr r1, VAL_ARM_IDLECT3
76 mov r1, #0x01 /* PER_EN bit */
77 ldr r0, REG_ARM_RSTCT2
78 strh r1, [r0] /* CLKM; Peripheral reset. */
80 /* Set CLKM to Sync-Scalable */
81 /* I supposedly need to enable the dsp clock before switching */
87 subs r0, r0, #0x1 /* wait for any bubbles to finish */
93 /* a few nops to let settle */
106 /* Ramp up the clock to 96Mhz */
107 ldr r1, VAL_DPLL1_CTL
108 ldr r0, REG_DPLL1_CTL
110 ands r1, r1, #0x10 /* Check if PLL is enabled. */
111 beq lock_end /* Do not look for lock if BYPASS selected */
114 ands r1, r1, #0x01 /* Check the LOCK bit.*/
115 beq 2b /* loop until bit goes hi. */
119 /*------------------------------------------------------*
120 * Turn off the watchdog during init... *
121 *------------------------------------------------------*/
123 ldr r1, WATCHDOG_VAL1
125 ldr r1, WATCHDOG_VAL2
147 /* Set memory timings corresponding to the new clock speed */
149 /* Check execution location to determine current execution location
150 * and branch to appropriate initialization code.
152 /* Load physical SDRAM base. */
154 /* Get current execution location. */
158 /* Skip over EMIF-fast initialization if running from SDRAM. */
162 * Delay for SDRAM initialization.
164 mov r3, #0x1800 /* value should be checked */
166 subs r3, r3, #0x1 /* Decrement count */
171 * Set SDRAM control values. Disable refresh before MRS command.
174 /* mobile ddr operation */
175 ldr r0, REG_SDRAM_OPERATION
179 /* config register */
180 ldr r0, REG_SDRAM_CONFIG
181 ldr r1, SDRAM_CONFIG_VAL
184 /* manual command register */
185 ldr r0, REG_SDRAM_MANUAL_CMD
186 /* issue set cke high */
187 mov r1, #CMD_SDRAM_CKE_SET_HIGH
190 mov r1, #CMD_SDRAM_NOP
196 bne waitMDDR1 /* delay loop */
198 /* issue precharge */
199 mov r1, #CMD_SDRAM_PRECHARGE
202 /* issue autorefresh x 2 */
203 mov r1, #CMD_SDRAM_AUTOREFRESH
207 /* mrs register ddr mobile */
208 ldr r0, REG_SDRAM_MRS
212 /* emrs1 low-power register */
213 ldr r0, REG_SDRAM_EMRS1
214 /* self refresh on all banks */
218 ldr r0, REG_DLL_URD_CONTROL
219 ldr r1, DLL_URD_CONTROL_VAL
222 ldr r0, REG_DLL_LRD_CONTROL
223 ldr r1, DLL_LRD_CONTROL_VAL
226 ldr r0, REG_DLL_WRT_CONTROL
227 ldr r1, DLL_WRT_CONTROL_VAL
237 * Delay for SDRAM initialization.
241 subs r3, r3, #1 /* Decrement count. */
247 ldr r0, REG_SDRAM_CONFIG
248 ldr r1, SDRAM_CONFIG_VAL
253 ldr r1, VAL_TC_EMIFS_CS0_CONFIG
254 ldr r0, REG_TC_EMIFS_CS0_CONFIG
255 str r1, [r0] /* Chip Select 0 */
257 ldr r1, VAL_TC_EMIFS_CS1_CONFIG
258 ldr r0, REG_TC_EMIFS_CS1_CONFIG
259 str r1, [r0] /* Chip Select 1 */
260 ldr r1, VAL_TC_EMIFS_CS3_CONFIG
261 ldr r0, REG_TC_EMIFS_CS3_CONFIG
262 str r1, [r0] /* Chip Select 3 */
264 #ifdef CONFIG_H2_OMAP1610
265 /* inserting additional 2 clock cycle hold time for LAN */
266 ldr r0, REG_TC_EMIFS_CS1_ADVANCED
267 ldr r1, VAL_TC_EMIFS_CS1_ADVANCED
270 /* Start MPU Timer 1 */
271 ldr r0, REG_MPU_LOAD_TIMER
272 ldr r1, VAL_MPU_LOAD_TIMER
275 ldr r0, REG_MPU_CNTL_TIMER
276 ldr r1, VAL_MPU_CNTL_TIMER
279 /* back to arch calling code */
282 /* the literal pools origin */
286 REG_TC_EMIFS_CONFIG: /* 32 bits */
288 REG_TC_EMIFS_CS0_CONFIG: /* 32 bits */
290 REG_TC_EMIFS_CS1_CONFIG: /* 32 bits */
292 REG_TC_EMIFS_CS2_CONFIG: /* 32 bits */
294 REG_TC_EMIFS_CS3_CONFIG: /* 32 bits */
297 #ifdef CONFIG_H2_OMAP1610
298 REG_TC_EMIFS_CS1_ADVANCED: /* 32 bits */
302 /* MPU clock/reset/power mode control registers */
303 REG_ARM_CKCTL: /* 16 bits */
306 REG_ARM_IDLECT3: /* 16 bits */
308 REG_ARM_IDLECT2: /* 16 bits */
310 REG_ARM_IDLECT1: /* 16 bits */
313 REG_ARM_RSTCT2: /* 16 bits */
315 REG_ARM_SYSST: /* 16 bits */
317 /* DPLL control registers */
318 REG_DPLL1_CTL: /* 16 bits */
321 /* Watch Dog register */
322 /* secure watchdog stop */
325 /* watchdog write pending */
334 /* SDRAM config is: auto refresh enabled, 16 bit 4 bank,
335 counter @8192 rows, 10 ns, 8 burst */
339 /* Operation register */
343 /* Manual command register */
344 REG_SDRAM_MANUAL_CMD:
347 /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
351 /* SDRAM MRS (New) config is: CAS latency is 2, burst length 8 */
355 /* WRT DLL register */
361 /* URD DLL register */
367 /* LRD DLL register */
379 /* 96 MHz Samsung Mobile DDR */
391 #ifdef CONFIG_OSK_OMAP5912
392 VAL_TC_EMIFS_CS0_CONFIG:
394 VAL_TC_EMIFS_CS1_CONFIG:
396 VAL_TC_EMIFS_CS2_CONFIG:
398 VAL_TC_EMIFS_CS3_CONFIG:
402 #ifdef CONFIG_H2_OMAP1610
403 VAL_TC_EMIFS_CS0_CONFIG:
405 VAL_TC_EMIFS_CS1_CONFIG:
407 VAL_TC_EMIFS_CS2_CONFIG:
409 VAL_TC_EMIFS_CS3_CONFIG:
411 VAL_TC_EMIFS_CS1_ADVANCED:
415 VAL_TC_EMIFF_SDRAM_CONFIG:
439 .equ CMD_SDRAM_NOP, 0x00000000
440 .equ CMD_SDRAM_PRECHARGE, 0x00000001
441 .equ CMD_SDRAM_AUTOREFRESH, 0x00000002
442 .equ CMD_SDRAM_CKE_SET_HIGH, 0x00000007