git.sur5r.net Git - u-boot/blob - board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c

   1 /******************************************************************************
   2 * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
   3 * (c) Copyright 2017 Opal Kelly Inc.
   4 *
   5 * SPDX-License-Identifier: GPL-2.0+
   6  *****************************************************************************/
   7
   8 #include "ps7_init_gpl.h"
   9 #include "asm/io.h"
  10
  11 unsigned long ps7_pll_init_data_3_0[] = {
  12         EMIT_WRITE(0XF8000008, 0x0000DF0DU),
  13         EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U, 0x001772C0U),
  14         EMIT_MASKWRITE(0XF8000100, 0x0007F000U, 0x0001A000U),
  15         EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000010U),
  16         EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000001U),
  17         EMIT_MASKWRITE(0XF8000100, 0x00000001U, 0x00000000U),
  18         EMIT_MASKPOLL(0XF800010C, 0x00000001U),
  19         EMIT_MASKWRITE(0XF8000100, 0x00000010U, 0x00000000U),
  20         EMIT_MASKWRITE(0XF8000120, 0x1F003F30U, 0x1F000200U),
  21         EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U, 0x001DB2C0U),
  22         EMIT_MASKWRITE(0XF8000104, 0x0007F000U, 0x00015000U),
  23         EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000010U),
  24         EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000001U),
  25         EMIT_MASKWRITE(0XF8000104, 0x00000001U, 0x00000000U),
  26         EMIT_MASKPOLL(0XF800010C, 0x00000002U),
  27         EMIT_MASKWRITE(0XF8000104, 0x00000010U, 0x00000000U),
  28         EMIT_MASKWRITE(0XF8000124, 0xFFF00003U, 0x0C200003U),
  29         EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U, 0x001F42C0U),
  30         EMIT_MASKWRITE(0XF8000108, 0x0007F000U, 0x00014000U),
  31         EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000010U),
  32         EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000001U),
  33         EMIT_MASKWRITE(0XF8000108, 0x00000001U, 0x00000000U),
  34         EMIT_MASKPOLL(0XF800010C, 0x00000004U),
  35         EMIT_MASKWRITE(0XF8000108, 0x00000010U, 0x00000000U),
  36         EMIT_WRITE(0XF8000004, 0x0000767BU),
  37         EMIT_EXIT(),
  38 };
  39
  40 unsigned long ps7_clock_init_data_3_0[] = {
  41         EMIT_WRITE(0XF8000008, 0x0000DF0DU),
  42         EMIT_MASKWRITE(0XF8000128, 0x03F03F01U, 0x00203401U),
  43         EMIT_MASKWRITE(0XF8000138, 0x00000011U, 0x00000001U),
  44         EMIT_MASKWRITE(0XF8000140, 0x03F03F71U, 0x00100801U),
  45         EMIT_MASKWRITE(0XF800014C, 0x00003F31U, 0x00000501U),
  46         EMIT_MASKWRITE(0XF8000150, 0x00003F33U, 0x00000A01U),
  47         EMIT_MASKWRITE(0XF8000154, 0x00003F33U, 0x00000A01U),
  48         EMIT_MASKWRITE(0XF8000168, 0x00003F31U, 0x00000501U),
  49         EMIT_MASKWRITE(0XF8000170, 0x03F03F30U, 0x00400500U),
  50         EMIT_MASKWRITE(0XF80001C4, 0x00000001U, 0x00000001U),
  51         EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU, 0x01DC044DU),
  52         EMIT_WRITE(0XF8000004, 0x0000767BU),
  53         EMIT_EXIT(),
  54 };
  55
  56 unsigned long ps7_ddr_init_data_3_0[] = {
  57         EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000080U),
  58         EMIT_MASKWRITE(0XF8006004, 0x0007FFFFU, 0x00001081U),
  59         EMIT_MASKWRITE(0XF8006008, 0x03FFFFFFU, 0x03C0780FU),
  60         EMIT_MASKWRITE(0XF800600C, 0x03FFFFFFU, 0x02001001U),
  61         EMIT_MASKWRITE(0XF8006010, 0x03FFFFFFU, 0x00014001U),
  62         EMIT_MASKWRITE(0XF8006014, 0x001FFFFFU, 0x0004281AU),
  63         EMIT_MASKWRITE(0XF8006018, 0xF7FFFFFFU, 0x44E458D2U),
  64         EMIT_MASKWRITE(0XF800601C, 0xFFFFFFFFU, 0x720238E5U),
  65         EMIT_MASKWRITE(0XF8006020, 0x7FDFFFFCU, 0x270872D0U),
  66         EMIT_MASKWRITE(0XF8006024, 0x0FFFFFC3U, 0x00000000U),
  67         EMIT_MASKWRITE(0XF8006028, 0x00003FFFU, 0x00002007U),
  68         EMIT_MASKWRITE(0XF800602C, 0xFFFFFFFFU, 0x00000008U),
  69         EMIT_MASKWRITE(0XF8006030, 0xFFFFFFFFU, 0x00040930U),
  70         EMIT_MASKWRITE(0XF8006034, 0x13FF3FFFU, 0x000116D4U),
  71         EMIT_MASKWRITE(0XF8006038, 0x00000003U, 0x00000000U),
  72         EMIT_MASKWRITE(0XF800603C, 0x000FFFFFU, 0x00000777U),
  73         EMIT_MASKWRITE(0XF8006040, 0xFFFFFFFFU, 0xFFF00000U),
  74         EMIT_MASKWRITE(0XF8006044, 0x0FFFFFFFU, 0x0F666666U),
  75         EMIT_MASKWRITE(0XF8006048, 0x0003F03FU, 0x0003C008U),
  76         EMIT_MASKWRITE(0XF8006050, 0xFF0F8FFFU, 0x77010800U),
  77         EMIT_MASKWRITE(0XF8006058, 0x00010000U, 0x00000000U),
  78         EMIT_MASKWRITE(0XF800605C, 0x0000FFFFU, 0x00005003U),
  79         EMIT_MASKWRITE(0XF8006060, 0x000017FFU, 0x0000003EU),
  80         EMIT_MASKWRITE(0XF8006064, 0x00021FE0U, 0x00020000U),
  81         EMIT_MASKWRITE(0XF8006068, 0x03FFFFFFU, 0x00284141U),
  82         EMIT_MASKWRITE(0XF800606C, 0x0000FFFFU, 0x00001610U),
  83         EMIT_MASKWRITE(0XF8006078, 0x03FFFFFFU, 0x00466111U),
  84         EMIT_MASKWRITE(0XF800607C, 0x000FFFFFU, 0x00032222U),
  85         EMIT_MASKWRITE(0XF80060A4, 0xFFFFFFFFU, 0x10200802U),
  86         EMIT_MASKWRITE(0XF80060A8, 0x0FFFFFFFU, 0x0690CB73U),
  87         EMIT_MASKWRITE(0XF80060AC, 0x000001FFU, 0x000001FEU),
  88         EMIT_MASKWRITE(0XF80060B0, 0x1FFFFFFFU, 0x1CFFFFFFU),
  89         EMIT_MASKWRITE(0XF80060B4, 0x00000200U, 0x00000200U),
  90         EMIT_MASKWRITE(0XF80060B8, 0x01FFFFFFU, 0x00200066U),
  91         EMIT_MASKWRITE(0XF80060C4, 0x00000003U, 0x00000000U),
  92         EMIT_MASKWRITE(0XF80060C8, 0x000000FFU, 0x00000000U),
  93         EMIT_MASKWRITE(0XF80060DC, 0x00000001U, 0x00000000U),
  94         EMIT_MASKWRITE(0XF80060F0, 0x0000FFFFU, 0x00000000U),
  95         EMIT_MASKWRITE(0XF80060F4, 0x0000000FU, 0x00000008U),
  96         EMIT_MASKWRITE(0XF8006114, 0x000000FFU, 0x00000000U),
  97         EMIT_MASKWRITE(0XF8006118, 0x7FFFFFCFU, 0x40000001U),
  98         EMIT_MASKWRITE(0XF800611C, 0x7FFFFFCFU, 0x40000001U),
  99         EMIT_MASKWRITE(0XF8006120, 0x7FFFFFCFU, 0x40000001U),
 100         EMIT_MASKWRITE(0XF8006124, 0x7FFFFFCFU, 0x40000001U),
 101         EMIT_MASKWRITE(0XF800612C, 0x000FFFFFU, 0x00029000U),
 102         EMIT_MASKWRITE(0XF8006130, 0x000FFFFFU, 0x00029000U),
 103         EMIT_MASKWRITE(0XF8006134, 0x000FFFFFU, 0x00029000U),
 104         EMIT_MASKWRITE(0XF8006138, 0x000FFFFFU, 0x00029000U),
 105         EMIT_MASKWRITE(0XF8006140, 0x000FFFFFU, 0x00000035U),
 106         EMIT_MASKWRITE(0XF8006144, 0x000FFFFFU, 0x00000035U),
 107         EMIT_MASKWRITE(0XF8006148, 0x000FFFFFU, 0x00000035U),
 108         EMIT_MASKWRITE(0XF800614C, 0x000FFFFFU, 0x00000035U),
 109         EMIT_MASKWRITE(0XF8006154, 0x000FFFFFU, 0x00000080U),
 110         EMIT_MASKWRITE(0XF8006158, 0x000FFFFFU, 0x00000080U),
 111         EMIT_MASKWRITE(0XF800615C, 0x000FFFFFU, 0x00000080U),
 112         EMIT_MASKWRITE(0XF8006160, 0x000FFFFFU, 0x00000080U),
 113         EMIT_MASKWRITE(0XF8006168, 0x001FFFFFU, 0x000000F9U),
 114         EMIT_MASKWRITE(0XF800616C, 0x001FFFFFU, 0x000000F9U),
 115         EMIT_MASKWRITE(0XF8006170, 0x001FFFFFU, 0x000000F9U),
 116         EMIT_MASKWRITE(0XF8006174, 0x001FFFFFU, 0x000000F9U),
 117         EMIT_MASKWRITE(0XF800617C, 0x000FFFFFU, 0x000000C0U),
 118         EMIT_MASKWRITE(0XF8006180, 0x000FFFFFU, 0x000000C0U),
 119         EMIT_MASKWRITE(0XF8006184, 0x000FFFFFU, 0x000000C0U),
 120         EMIT_MASKWRITE(0XF8006188, 0x000FFFFFU, 0x000000C0U),
 121         EMIT_MASKWRITE(0XF8006190, 0x6FFFFEFEU, 0x00040080U),
 122         EMIT_MASKWRITE(0XF8006194, 0x000FFFFFU, 0x0001FC82U),
 123         EMIT_MASKWRITE(0XF8006204, 0xFFFFFFFFU, 0x00000000U),
 124         EMIT_MASKWRITE(0XF8006208, 0x000703FFU, 0x000003FFU),
 125         EMIT_MASKWRITE(0XF800620C, 0x000703FFU, 0x000003FFU),
 126         EMIT_MASKWRITE(0XF8006210, 0x000703FFU, 0x000003FFU),
 127         EMIT_MASKWRITE(0XF8006214, 0x000703FFU, 0x000003FFU),
 128         EMIT_MASKWRITE(0XF8006218, 0x000F03FFU, 0x000003FFU),
 129         EMIT_MASKWRITE(0XF800621C, 0x000F03FFU, 0x000003FFU),
 130         EMIT_MASKWRITE(0XF8006220, 0x000F03FFU, 0x000003FFU),
 131         EMIT_MASKWRITE(0XF8006224, 0x000F03FFU, 0x000003FFU),
 132         EMIT_MASKWRITE(0XF80062A8, 0x00000FF5U, 0x00000000U),
 133         EMIT_MASKWRITE(0XF80062AC, 0xFFFFFFFFU, 0x00000000U),
 134         EMIT_MASKWRITE(0XF80062B0, 0x003FFFFFU, 0x00005125U),
 135         EMIT_MASKWRITE(0XF80062B4, 0x0003FFFFU, 0x000012A8U),
 136         EMIT_MASKPOLL(0XF8000B74, 0x00002000U),
 137         EMIT_MASKWRITE(0XF8006000, 0x0001FFFFU, 0x00000081U),
 138         EMIT_MASKPOLL(0XF8006054, 0x00000007U),
 139         EMIT_EXIT(),
 140 };
 141
 142 unsigned long ps7_mio_init_data_3_0[] = {
 143         EMIT_WRITE(0XF8000008, 0x0000DF0DU),
 144         EMIT_MASKWRITE(0XF8000B40, 0x00000FFFU, 0x00000600U),
 145         EMIT_MASKWRITE(0XF8000B44, 0x00000FFFU, 0x00000600U),
 146         EMIT_MASKWRITE(0XF8000B48, 0x00000FFFU, 0x00000672U),
 147         EMIT_MASKWRITE(0XF8000B4C, 0x00000FFFU, 0x00000672U),
 148         EMIT_MASKWRITE(0XF8000B50, 0x00000FFFU, 0x00000674U),
 149         EMIT_MASKWRITE(0XF8000B54, 0x00000FFFU, 0x00000674U),
 150         EMIT_MASKWRITE(0XF8000B58, 0x00000FFFU, 0x00000600U),
 151         EMIT_MASKWRITE(0XF8000B5C, 0xFFFFFFFFU, 0x0018C61CU),
 152         EMIT_MASKWRITE(0XF8000B60, 0xFFFFFFFFU, 0x00F9861CU),
 153         EMIT_MASKWRITE(0XF8000B64, 0xFFFFFFFFU, 0x00F9861CU),
 154         EMIT_MASKWRITE(0XF8000B68, 0xFFFFFFFFU, 0x00F9861CU),
 155         EMIT_MASKWRITE(0XF8000B6C, 0x00007FFFU, 0x00000260U),
 156         EMIT_MASKWRITE(0XF8000B70, 0x00000001U, 0x00000001U),
 157         EMIT_MASKWRITE(0XF8000B70, 0x00000021U, 0x00000020U),
 158         EMIT_MASKWRITE(0XF8000B70, 0x07FEFFFFU, 0x00000823U),
 159         EMIT_MASKWRITE(0XF8000700, 0x00003FFFU, 0x00001600U),
 160         EMIT_MASKWRITE(0XF8000704, 0x00003FFFU, 0x00001602U),
 161         EMIT_MASKWRITE(0XF8000708, 0x00003FFFU, 0x00000602U),
 162         EMIT_MASKWRITE(0XF800070C, 0x00003FFFU, 0x00000602U),
 163         EMIT_MASKWRITE(0XF8000710, 0x00003FFFU, 0x00000602U),
 164         EMIT_MASKWRITE(0XF8000714, 0x00003FFFU, 0x00000602U),
 165         EMIT_MASKWRITE(0XF8000718, 0x00003FFFU, 0x00000602U),
 166         EMIT_MASKWRITE(0XF800071C, 0x00003FFFU, 0x00000600U),
 167         EMIT_MASKWRITE(0XF8000720, 0x00003FFFU, 0x00000600U),
 168         EMIT_MASKWRITE(0XF8000724, 0x00003FFFU, 0x00001600U),
 169         EMIT_MASKWRITE(0XF8000728, 0x00003FFFU, 0x00001600U),
 170         EMIT_MASKWRITE(0XF800072C, 0x00003FFFU, 0x00001600U),
 171         EMIT_MASKWRITE(0XF8000730, 0x00003FFFU, 0x00001640U),
 172         EMIT_MASKWRITE(0XF8000734, 0x00003FFFU, 0x00001640U),
 173         EMIT_MASKWRITE(0XF8000738, 0x00003FFFU, 0x000016E1U),
 174         EMIT_MASKWRITE(0XF800073C, 0x00003FFFU, 0x000016E0U),
 175         EMIT_MASKWRITE(0XF8000740, 0x00003FFFU, 0x00001202U),
 176         EMIT_MASKWRITE(0XF8000744, 0x00003FFFU, 0x00001202U),
 177         EMIT_MASKWRITE(0XF8000748, 0x00003FFFU, 0x00001202U),
 178         EMIT_MASKWRITE(0XF800074C, 0x00003FFFU, 0x00001202U),
 179         EMIT_MASKWRITE(0XF8000750, 0x00003FFFU, 0x00001202U),
 180         EMIT_MASKWRITE(0XF8000754, 0x00003FFFU, 0x00001202U),
 181         EMIT_MASKWRITE(0XF8000758, 0x00003FFFU, 0x00001203U),
 182         EMIT_MASKWRITE(0XF800075C, 0x00003FFFU, 0x00001203U),
 183         EMIT_MASKWRITE(0XF8000760, 0x00003FFFU, 0x00001203U),
 184         EMIT_MASKWRITE(0XF8000764, 0x00003FFFU, 0x00001203U),
 185         EMIT_MASKWRITE(0XF8000768, 0x00003FFFU, 0x00001203U),
 186         EMIT_MASKWRITE(0XF800076C, 0x00003FFFU, 0x00001203U),
 187         EMIT_MASKWRITE(0XF8000770, 0x00003FFFU, 0x00001204U),
 188         EMIT_MASKWRITE(0XF8000774, 0x00003FFFU, 0x00001205U),
 189         EMIT_MASKWRITE(0XF8000778, 0x00003FFFU, 0x00001204U),
 190         EMIT_MASKWRITE(0XF800077C, 0x00003FFFU, 0x00001205U),
 191         EMIT_MASKWRITE(0XF8000780, 0x00003FFFU, 0x00001204U),
 192         EMIT_MASKWRITE(0XF8000784, 0x00003FFFU, 0x00001204U),
 193         EMIT_MASKWRITE(0XF8000788, 0x00003FFFU, 0x00001204U),
 194         EMIT_MASKWRITE(0XF800078C, 0x00003FFFU, 0x00001204U),
 195         EMIT_MASKWRITE(0XF8000790, 0x00003FFFU, 0x00001205U),
 196         EMIT_MASKWRITE(0XF8000794, 0x00003FFFU, 0x00001204U),
 197         EMIT_MASKWRITE(0XF8000798, 0x00003FFFU, 0x00001204U),
 198         EMIT_MASKWRITE(0XF800079C, 0x00003FFFU, 0x00001204U),
 199         EMIT_MASKWRITE(0XF80007A0, 0x00003FFFU, 0x00001280U),
 200         EMIT_MASKWRITE(0XF80007A4, 0x00003FFFU, 0x00001280U),
 201         EMIT_MASKWRITE(0XF80007A8, 0x00003FFFU, 0x00001280U),
 202         EMIT_MASKWRITE(0XF80007AC, 0x00003FFFU, 0x00001280U),
 203         EMIT_MASKWRITE(0XF80007B0, 0x00003FFFU, 0x00001280U),
 204         EMIT_MASKWRITE(0XF80007B4, 0x00003FFFU, 0x00001280U),
 205         EMIT_MASKWRITE(0XF80007B8, 0x00003F01U, 0x00001201U),
 206         EMIT_MASKWRITE(0XF80007BC, 0x00003FFFU, 0x00001200U),
 207         EMIT_MASKWRITE(0XF80007C0, 0x00003FFFU, 0x00001200U),
 208         EMIT_MASKWRITE(0XF80007C4, 0x00003FFFU, 0x00001200U),
 209         EMIT_MASKWRITE(0XF80007C8, 0x00003FFFU, 0x00001200U),
 210         EMIT_MASKWRITE(0XF80007CC, 0x00003FFFU, 0x00001200U),
 211         EMIT_MASKWRITE(0XF80007D0, 0x00003FFFU, 0x00001280U),
 212         EMIT_MASKWRITE(0XF80007D4, 0x00003FFFU, 0x00001280U),
 213         EMIT_MASKWRITE(0XF8000830, 0x003F003FU, 0x002E0037U),
 214         EMIT_WRITE(0XF8000004, 0x0000767BU),
 215         EMIT_EXIT(),
 216 };
 217
 218 unsigned long ps7_peripherals_init_data_3_0[] = {
 219         EMIT_WRITE(0XF8000008, 0x0000DF0DU),
 220         EMIT_MASKWRITE(0XF8000B48, 0x00000180U, 0x00000180U),
 221         EMIT_MASKWRITE(0XF8000B4C, 0x00000180U, 0x00000180U),
 222         EMIT_MASKWRITE(0XF8000B50, 0x00000180U, 0x00000180U),
 223         EMIT_MASKWRITE(0XF8000B54, 0x00000180U, 0x00000180U),
 224         EMIT_WRITE(0XF8000004, 0x0000767BU),
 225         EMIT_MASKWRITE(0XE0000034, 0x000000FFU, 0x00000006U),
 226         EMIT_MASKWRITE(0XE0000018, 0x0000FFFFU, 0x0000007CU),
 227         EMIT_MASKWRITE(0XE0000000, 0x000001FFU, 0x00000017U),
 228         EMIT_MASKWRITE(0XE0000004, 0x000003FFU, 0x00000020U),
 229         EMIT_MASKWRITE(0XE000D000, 0x00080000U, 0x00080000U),
 230         EMIT_MASKWRITE(0XF8007000, 0x20000000U, 0x00000000U),
 231         EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),
 232         EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF8000U),
 233         EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00088000U),
 234         EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF0000U),
 235         EMIT_MASKDELAY(0XF8F00200, 1),
 236         EMIT_MASKWRITE(0XE000A008, 0xFFFFFFFFU, 0x7FFF8000U),
 237         EMIT_MASKDELAY(0XF8F00200, 1),
 238         EMIT_MASKWRITE(0XE000A244, 0x003FFFFFU, 0x00088000U),
 239         EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370008U),
 240         EMIT_MASKWRITE(0XE000A248, 0x003FFFFFU, 0x00088000U),
 241         EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370000U),
 242         EMIT_MASKDELAY(0XF8F00200, 1),
 243         EMIT_MASKWRITE(0XE000A00C, 0x003F003FU, 0x00370008U),
 244         EMIT_MASKDELAY(0XF8F00200, 1),
 245         EMIT_MASKDELAY(0XF8F00200, 1),
 246         EMIT_MASKDELAY(0XF8F00200, 1),
 247         EMIT_EXIT(),
 248 };
 249
 250 unsigned long ps7_post_config_3_0[] = {
 251         EMIT_WRITE(0XF8000008, 0x0000DF0DU),
 252         EMIT_MASKWRITE(0XF8000900, 0x0000000FU, 0x0000000FU),
 253         EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU, 0x00000000U),
 254         EMIT_WRITE(0XF8000004, 0x0000767BU),
 255         EMIT_EXIT(),
 256 };
 257
 258
 259 unsigned long ps7_reset_apu_3_0[] = {
 260         EMIT_MASKWRITE(0xF8000244, 0x00000022U, 0x00000022U),
 261         EMIT_EXIT(),
 262 };
 263
 264 #define PS7_MASK_POLL_TIME 100000000
 265
 266 static inline void iowrite(unsigned long val, unsigned long addr)
 267 {
 268         __raw_writel(val, addr);
 269 }
 270
 271 static inline unsigned long ioread(unsigned long addr)
 272 {
 273         return __raw_readl(addr);
 274 }
 275
 276 int ps7_config(unsigned long *ps7_config_init)
 277 {
 278         unsigned long *ptr = ps7_config_init;
 279
 280         unsigned long opcode;   /* current instruction .. */
 281         unsigned long args[16]; /* no opcode has so many args ... */
 282         int numargs;            /* number of arguments of this instruction */
 283         int j;                  /* general purpose index */
 284
 285         unsigned long addr;
 286         unsigned long val, mask;
 287
 288         int finish = -1;        /* loop while this is negative ! */
 289         int i = 0;              /* Timeout variable */
 290
 291         while (finish < 0) {
 292                 numargs = ptr[0] & 0xF;
 293                 opcode = ptr[0] >> 4;
 294
 295                 for (j = 0; j < numargs; j++)
 296                         args[j] = ptr[j + 1];
 297                 ptr += numargs + 1;
 298
 299                 switch (opcode) {
 300                 case OPCODE_EXIT:
 301                         finish = PS7_INIT_SUCCESS;
 302                         break;
 303
 304                 case OPCODE_WRITE:
 305                         addr = args[0];
 306                         val = args[1];
 307                         iowrite(val, addr);
 308                         break;
 309
 310                 case OPCODE_MASKWRITE:
 311                         addr = args[0];
 312                         mask = args[1];
 313                         val = args[2];
 314                         iowrite((val & mask) | (ioread(addr) & ~mask) , addr);
 315                         break;
 316
 317                 case OPCODE_MASKPOLL:
 318                         addr = args[0];
 319                         mask = args[1];
 320                         i = 0;
 321                         while (!(ioread(addr) & mask)) {
 322                                 if (i == PS7_MASK_POLL_TIME) {
 323                                         finish = PS7_INIT_TIMEOUT;
 324                                         break;
 325                                 }
 326                                 i++;
 327                         }
 328                         break;
 329                 case OPCODE_MASKDELAY:
 330                         addr = args[0];
 331                         mask = args[1];
 332                         int delay = get_number_of_cycles_for_delay(mask);
 333                         perf_reset_and_start_timer();
 334                         while (ioread(addr) < delay)
 335                                 ;
 336                         break;
 337                 default:
 338                         finish = PS7_INIT_CORRUPT;
 339                         break;
 340                 }
 341         }
 342         return finish;
 343 }
 344
 345 int ps7_post_config(void)
 346 {
 347         return ps7_config(ps7_post_config_3_0);
 348 }
 349
 350 int ps7_init(void)
 351 {
 352         int ret;
 353
 354         ret = ps7_config(ps7_reset_apu_3_0);
 355         if (ret != PS7_INIT_SUCCESS)
 356                 return ret;
 357
 358         ret = ps7_config(ps7_mio_init_data_3_0);
 359         if (ret != PS7_INIT_SUCCESS)
 360                 return ret;
 361
 362         ret = ps7_config(ps7_pll_init_data_3_0);
 363         if (ret != PS7_INIT_SUCCESS)
 364                 return ret;
 365
 366         ret = ps7_config(ps7_clock_init_data_3_0);
 367         if (ret != PS7_INIT_SUCCESS)
 368                 return ret;
 369
 370         ret = ps7_config(ps7_ddr_init_data_3_0);
 371         if (ret != PS7_INIT_SUCCESS)
 372                 return ret;
 373
 374         ret = ps7_config(ps7_peripherals_init_data_3_0);
 375         if (ret != PS7_INIT_SUCCESS)
 376                 return ret;
 377         return PS7_INIT_SUCCESS;
 378 }
 379
 380 /* For delay calculation using global timer */
 381
 382 /* start timer */
 383 void perf_start_clock(void)
 384 {
 385         iowrite((1 << 0) | /* Timer Enable */
 386                 (1 << 3) | /* Auto-increment */
 387                 (0 << 8),  /* Pre-scale */
 388                 SCU_GLOBAL_TIMER_CONTROL);
 389 }
 390
 391 /* stop timer and reset timer count regs */
 392 void perf_reset_clock(void)
 393 {
 394         perf_disable_clock();
 395         iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32);
 396         iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32);
 397 }
 398
 399 /* Compute mask for given delay in miliseconds*/
 400 int get_number_of_cycles_for_delay(unsigned int delay)
 401 {
 402         return APU_FREQ * delay / (2 * 1000);
 403 }
 404
 405 /* stop timer */
 406 void perf_disable_clock(void)
 407 {
 408         iowrite(0, SCU_GLOBAL_TIMER_CONTROL);
 409 }
 410
 411 void perf_reset_and_start_timer(void)
 412 {
 413         perf_reset_clock();
 414         perf_start_clock();
 415 }