1 /* sim.cfg -- Simulator configuration script file
2 Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
4 This file is part of OpenRISC 1000 Architectural Simulator.
5 It contains the default configuration and help about configuring
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
25 The ork1sim has various parameters, that are set in configuration files
26 like this one. The user can switch between configurations at startup by
27 specifying the required configuration file with the -f <filename.cfg> option.
28 If no configuration file is specified or1ksim searches for the default
29 configuration file sim.cfg. First it searches for './sim.cfg'. If this
30 file is not found, it searches for '~/or1k/sim.cfg'. If this file is
31 not found too, it reverts to the built-in default configuration.
33 NOTE: Users should not rely on the built-in configuration, since the
34 default configuration may differ between version.
35 Rather create a configuration file that sets all critical values.
37 This file may contain (standard C) comments only - no // support.
39 Configure files may be be included, using:
40 include "file_name_to_include"
42 Like normal configuration files, the included file is divided into
43 sections. Each section is described in detail also.
45 Some section have subsections. One example of such a subsection is:
48 instance specific parameters...
51 which creates a device instance.
57 This section specifies how the memory is generated and the blocks
60 type = random/unknown/pattern
61 Specifies the initial memory values.
62 'random' generates random memory using seed 'random_seed'.
63 'pattern' fills memory with 'pattern'.
64 'unknown' does not specify how memory should be generated,
65 leaving the memory in a undefined state. This is the fastest
69 random seed for randomizer, used if type = 'random'.
72 pattern to fill memory, used if type = 'pattern'.
75 number of memory instances connected
77 baseaddr = <hex_value>
87 chip enable index of the memory instance
90 memory controller this memory is connected to
93 cycles, required for read access, -1 if instance does not support reading
96 cycles, required for write access, -1 if instance does not support writing
99 filename, where to log memory accesses to, no log, if log command is not specified
105 type = unknown /* Fastest */
110 baseaddr = 0xf0000000
118 type = unknown /* Fastest */
123 baseaddr = 0x00000000
131 type = unknown /* Fastest */
136 baseaddr = 0xa4000000
145 This section configures the Instruction Memory Manangement Unit
150 (NOTE: UPR bit is set)
153 number of ITLB sets; must be power of two
159 instruction page size; must be power of two
162 instruction entry size in bytes
165 number of ITLB usage states (2, 3, 4 etc., max is 4)
168 number of cycles immu hit costs
171 number of cycles immu miss costs
186 This section configures the Data Memory Manangement Unit
191 (NOTE: UPR bit is set)
194 number of DTLB sets; must be power of two
200 data page size; must be power of two
203 data entry size in bytes
206 number of DTLB usage states (2, 3, 4 etc., max is 4)
209 number of cycles dmmu hit costs
212 number of cycles dmmu miss costs
227 This section configures the Instruction Cache
232 (NOTE: UPR bit is set)
235 number of IC sets; must be power of two
241 IC block size in bytes; must be power of two
244 number of IC usage states (2, 3, 4 etc., max is 4)
247 number of cycles ic hit costs
250 number of cycles ic miss costs
265 This section configures the Data Cache
270 (NOTE: UPR bit is set)
273 number of DC sets; must be power of two
279 DC block size in bytes; must be power of two
282 number of DC usage states (2, 3, 4 etc., max is 4)
284 load_hitdelay = <value>
285 number of cycles dc load hit costs
287 load_missdelay = <value>
288 number of cycles dc load miss costs
290 store_hitdelay = <value>
291 number of cycles dc load hit costs
293 store_missdelay = <value>
294 number of cycles dc load miss costs
311 This section specifies how or1ksim should behave.
314 '0': don't print extra messages
315 '1': print extra messages
318 0 : no debug messages
319 1-9: debug message level.
320 higher numbers produce more messages
323 '0': don't generate profiling file 'sim.profile'
324 '1': don't generate profiling file 'sim.profile'
326 prof_fn = "<filename>"
327 optional filename for the profiling file.
328 valid only if 'profile' is set
331 '0': don't generate memory profiling file 'sim.mprofile'
332 '1': generate memory profiling file 'sim.mprofile'
334 mprof_fn = "<filename>"
335 optional filename for the memory profiling file.
336 valid only if 'mprofile' is set
339 '0': don't track execution flow
340 '1': track execution flow
341 Execution flow can be tracked for the simulator's
342 'hist' command. Useful for back-trace debugging.
345 '0': start in <not interactive prompt> (so what do we start in ???)
346 '1': start in interactive prompt.
349 '0': don't generate execution log.
350 '1': generate execution log.
352 exe_log = default/hardware/simple/software
353 type of execution log, default is used when not specified
355 exe_log_start = <value>
356 index of first instruction to start logging, default = 0
358 exe_log_end = <value>
359 index of last instruction to end logging; not limited, if omitted
361 exe_log_marker = <value>
362 <value> specifies number of instructions before horizontal marker is
363 printed; if zero, markers are disabled (default)
365 exe_log_fn = "<filename>"
366 filename for the exection log file.
367 valid only if 'exe_log' is set
369 clkcycle = <value>[ps|ns|us|ms]
370 specifies time measurement for one cycle
385 This section configures the Verification API, used for Advanced
389 '0': disbable VAPI server
390 '1': enable/start VAPI server
392 server_port = <value>
393 TCP/IP port to start VAPI server on
396 '0': disable VAPI requests logging
397 '1': enable VAPI requests logging
400 '0': don't log device id (for compatability with old version)
405 filename for the log file.
406 valid only if log_enabled is set
413 vapi_log_fn = "vapi.log"
419 This section specifies various CPU parameters.
423 specifies version and revision of the CPU used
426 changes the upr register
429 sets the initial Supervision Register value
430 supervisor mode (SM) and fixed one (FO) set = 0x8001
431 exception prefix high (EPH, vectors@0xf0000000) = 0x4000
432 together, (SM | FO | EPH) = 0xc001
435 '1': CPU is superscalar
436 (modify cpu/or32/execute.c to tune superscalar model)
439 '0': don't track data hazards in superscalar CPU
440 '1': track data hazards in superscalar CPU
441 If tracked, data hazards can be displayed using the
442 simulator's 'r' command.
445 '0': don't calculate inter-instruction dependencies.
446 '1': calculate inter-instruction dependencies.
447 If calculated, inter-instruction dependencies can be
448 displayed using the simulator's 'stat' command.
451 length of store buffer (<= 256), 0 = disabled
458 sr = 0x8001 /*SPR_SR_FO | SPR_SR_SM | SPR_SR_EPH */
469 This section specifies Power Management parameters
472 '0': disable power management
473 '1': enable power management
483 This section specifies how branch prediction should behave.
486 '0': disable branch prediction
487 '1': enable branch prediction
490 '0': disable branch target instruction cache model
491 '1': enable branch target instruction cache model
494 Static branch prediction for 'l.bf'
495 '0': don't use forward prediction
496 '1': use forward prediction
499 Static branch prediction for 'l.bnf'
500 '0': don't use forward prediction
501 '1': use forward prediction
504 number of cycles bpb hit costs
507 number of cycles bpb miss costs
522 This sections specifies how the debug unit should behave.
525 '0': disable debug unit
526 '1': enable debug unit
529 '0': don't start gdb server
530 '1': start gdb server at port 'server_port'
532 server_port = <value>
533 TCP/IP port to start gdb server on
534 valid only if gdb_enabled is set
536 vapi_id = <hex_value>
537 Used to create "fake" vapi log file containing the JTAG proxy messages.
541 /* gdb_enabled = 0 */
542 /* server_port = 9999*/
550 This section configures the memory controller
553 '0': disable memory controller
554 '1': enable memory controller
556 baseaddr = <hex_value>
557 address of first MC register
560 Power On Configuration register
563 Index of this memory controller amongst all the memory controllers
568 baseaddr = 0x93000000
569 POC = 0x00000008 /* Power on configuration register */
576 This section configures the UARTs
579 Enable/disable the peripheral. By default if it is enabled.
581 baseaddr = <hex_value>
582 address of first UART register for this device
585 channel = <channeltype>:<args>
587 The channel parameter indicates the source of received UART characters
588 and the sink for transmitted UART characters.
590 The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
593 A) To send/receive characters from a pair of files, use a file
596 channel=file:<rxfile>,<txfile>
598 B) To create an interactive terminal window, use an xterm channel:
600 channel=xterm:[<xterm_arg>]*
602 C) To create a bidirectional tcp socket which one could, for example,
603 access via telnet, use a tcp channel:
605 channel=tcp:<port number>
607 D) To cause the UART to read/write from existing numeric file
608 descriptors, use an fd channel:
610 channel=fd:<rx file descriptor num>,<tx file descriptor num>
612 E) To connect the UART to a physical serial port, create a tty
615 channel=tty:device=/dev/ttyS0,baud=9600
618 irq number for this device
621 '0': this device is a UART16450
622 '1': this device is a UART16550
625 in msecs... time to block, -1 to disable it
627 vapi_id = <hex_value>
628 VAPI id of this instance
633 baseaddr = 0x90000000
635 /* channel = "file:uart0.rx,uart0.tx" */
636 /* channel = "tcp:10084" */
638 jitter = -1 /* async behaviour */
645 This section configures the DMAs
648 Enable/disable the peripheral. By default if it is enabled.
650 baseaddr = <hex_value>
651 address of first DMA register for this device
654 irq number for this device
656 vapi_id = <hex_value>
657 VAPI id of this instance
662 baseaddr = 0x9a000000
669 This section configures the ETHERNETs
672 Enable/disable the peripheral. By default if it is enabled.
674 baseaddr = <hex_value>
675 address of first ethernet register for this device
678 which controller is this ethernet "connected" to
681 ethernet mac IRQ level
684 use 0 - file interface, 1 - socket interface
687 DMA channel used for RX
690 DMA channel used for TX
692 rxfile = "<filename>"
693 filename, where to read data from
695 txfile = "<filename>"
696 filename, where to write data to
698 sockif = "<ifacename>"
699 interface name of ethernet socket
701 vapi_id = <hex_value>
702 VAPI id of this instance
707 baseaddr = 0x92000000
722 This section configures the GPIOs
725 Enable/disable the peripheral. By default if it is enabled.
727 baseaddr = <hex_value>
728 address of first GPIO register for this device
731 irq number for this device
733 base_vapi_id = <hex_value>
734 first VAPI id of this instance
735 GPIO uses 8 consecutive VAPI IDs
740 baseaddr = 0x91000000
742 base_vapi_id = 0x0200
747 This section configures the VGA/LCD controller
750 Enable/disable the peripheral. By default if it is enabled.
752 baseaddr = <hex_value>
753 address of first VGA register
756 irq number for this device
758 refresh_rate = <value>
759 number of cycles between screen dumps
761 filename = "<filename>"
762 template name for generated names (e.g. "primary" produces "primary0023.bmp")
767 baseaddr = 0x97100000
769 refresh_rate = 100000
774 /* TICK TIMER SECTION
776 This section configures tick timer
779 whether tick timer is enabled
789 This section configures the frame buffer
792 Enable/disable the peripheral. By default if it is enabled.
794 baseaddr = <hex_value>
795 base address of frame buffer
797 paladdr = <hex_value>
798 base address of first palette entry
800 refresh_rate = <value>
801 number of cycles between screen dumps
803 filename = "<filename>"
804 template name for generated names (e.g. "primary" produces "primary0023.bmp")
809 baseaddr = 0x97000000
810 refresh_rate = 1000000
817 This section configures the PS/2 compatible keyboard
819 baseaddr = <hex_value>
820 base address of the keyboard device
822 rxfile = "<filename>"
823 filename, where to read data from
829 baseaddr = 0x94000000
836 This section configures the ATA/ATAPI host controller
838 baseaddr = <hex_value>
839 address of first ATA register
842 Enable/disable the peripheral. By default if it is enabled.
845 irq number for this device
848 debug level for ata models.
851 3: normal messages (more messages than verbose)
852 5: debug messages (normal debug messages)
853 7: flow control messages (debug statemachine flows)
854 9: low priority message (display everything the code does)
856 dev_type0/1 = <value>
858 0: NO_CONNeCT: none (not connected)
859 1: FILE : simulated harddisk
860 2: LOCAL : local system harddisk
862 dev_file0/1 = "<filename>"
863 filename for simulated ATA device
864 valid only if dev_type0 == 1
866 dev_size0/1 = <value>
867 size of simulated hard-disk (in MBytes)
868 valid only if dev_type0 == 1
870 dev_packet0/1 = <value>
871 0: simulated ATA device does NOT implement PACKET command feature set
872 1: simulated ATA device does implement PACKET command feature set
879 baseaddr = 0x9e000000