2 * Maintainer : Steve Sakoman <steve@sakoman.com>
4 * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
5 * Richard Woodruff <r-woodruff2@ti.com>
6 * Syed Mohammed Khasim <khasim@ti.com>
7 * Sunil Kumar <sunilsaini05@gmail.com>
8 * Shashi Ranjan <shashiranjanmca05@gmail.com>
10 * (C) Copyright 2004-2008
11 * Texas Instruments, <www.ti.com>
13 * SPDX-License-Identifier: GPL-2.0+
18 #include <linux/mtd/nand.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/mux.h>
22 #include <asm/arch/mem.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm/omap_gpmc.h>
26 #include <asm/mach-types.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 #define TWL4030_I2C_BUS 0
32 #define EXPANSION_EEPROM_I2C_BUS 2
33 #define EXPANSION_EEPROM_I2C_ADDRESS 0x51
35 #define GUMSTIX_SUMMIT 0x01000200
36 #define GUMSTIX_TOBI 0x02000200
37 #define GUMSTIX_TOBI_DUO 0x03000200
38 #define GUMSTIX_PALO35 0x04000200
39 #define GUMSTIX_PALO43 0x05000200
40 #define GUMSTIX_CHESTNUT43 0x06000200
41 #define GUMSTIX_PINTO 0x07000200
42 #define GUMSTIX_GALLOP43 0x08000200
44 #define ETTUS_USRP_E 0x01000300
46 #define GUMSTIX_NO_EEPROM 0xffffffff
49 unsigned int device_vendor;
50 unsigned char revision;
51 unsigned char content;
57 #if defined(CONFIG_CMD_NET)
58 static void setup_net_chip(void);
61 /* GPMC definitions for LAN9221 chips on Tobi expansion boards */
62 static const u32 gpmc_lan_config[] = {
63 NET_LAN9221_GPMC_CONFIG1,
64 NET_LAN9221_GPMC_CONFIG2,
65 NET_LAN9221_GPMC_CONFIG3,
66 NET_LAN9221_GPMC_CONFIG4,
67 NET_LAN9221_GPMC_CONFIG5,
68 NET_LAN9221_GPMC_CONFIG6,
69 /*CONFIG7- computed as params */
74 * Description: Early hardware init.
78 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
79 /* board id for Linux */
80 gd->bd->bi_arch_number = MACH_TYPE_OVERO;
82 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
88 * Routine: get_board_revision
89 * Description: Returns the board revision
91 int get_board_revision(void)
95 #ifdef CONFIG_DRIVER_OMAP34XX_I2C
98 /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */
99 /* these boards should return a revision number of 0 */
100 /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */
101 i2c_set_bus_num(TWL4030_I2C_BUS);
103 i2c_write(0x4B, 0x29, 1, &data, 1);
105 i2c_write(0x4B, 0x2b, 1, &data, 1);
106 i2c_read(0x4B, 0x2a, 1, &data, 1);
109 if (!gpio_request(112, "") &&
110 !gpio_request(113, "") &&
111 !gpio_request(115, "")) {
113 gpio_direction_input(112);
114 gpio_direction_input(113);
115 gpio_direction_input(115);
117 revision = gpio_get_value(115) << 2 |
118 gpio_get_value(113) << 1 |
121 puts("Error: unable to acquire board revision GPIOs\n");
128 #ifdef CONFIG_SPL_BUILD
130 * Routine: get_board_mem_timings
131 * Description: If we use SPL then there is no x-loader nor config header
132 * so we have to setup the DDR timings ourself on both banks.
134 void get_board_mem_timings(struct board_sdrc_timings *timings)
136 timings->mr = MICRON_V_MR_165;
137 switch (get_board_revision()) {
138 case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */
139 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
140 timings->ctrla = MICRON_V_ACTIMA_165;
141 timings->ctrlb = MICRON_V_ACTIMB_165;
142 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
144 case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */
145 timings->mcfg = MICRON_V_MCFG_200(256 << 20);
146 timings->ctrla = MICRON_V_ACTIMA_200;
147 timings->ctrlb = MICRON_V_ACTIMB_200;
148 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
150 case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */
151 timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
152 timings->ctrla = HYNIX_V_ACTIMA_200;
153 timings->ctrlb = HYNIX_V_ACTIMB_200;
154 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
156 case REVISION_3: /* Micron 512MB/1024MB, 1/2 banks of 512MB */
157 timings->mcfg = MCFG(512 << 20, 15);
158 timings->ctrla = MICRON_V_ACTIMA_200;
159 timings->ctrlb = MICRON_V_ACTIMB_200;
160 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
163 timings->mcfg = MICRON_V_MCFG_165(128 << 20);
164 timings->ctrla = MICRON_V_ACTIMA_165;
165 timings->ctrlb = MICRON_V_ACTIMB_165;
166 timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
172 * Routine: get_sdio2_config
173 * Description: Return information about the wifi module connection
174 * Returns 0 if the module connects though a level translator
175 * Returns 1 if the module connects directly
177 int get_sdio2_config(void)
181 if (!gpio_request(130, "") && !gpio_request(139, "")) {
183 gpio_direction_output(130, 0);
184 gpio_direction_input(139);
187 gpio_set_value(130, 0);
188 if (gpio_get_value(139) == 0) {
189 gpio_set_value(130, 1);
190 if (gpio_get_value(139) == 1)
194 gpio_direction_input(130);
196 puts("Error: unable to acquire sdio2 clk GPIOs\n");
204 * Routine: get_expansion_id
205 * Description: This function checks for expansion board by checking I2C
206 * bus 2 for the availability of an AT24C01B serial EEPROM.
207 * returns the device_vendor field from the EEPROM
209 unsigned int get_expansion_id(void)
211 i2c_set_bus_num(EXPANSION_EEPROM_I2C_BUS);
213 /* return GUMSTIX_NO_EEPROM if eeprom doesn't respond */
214 if (i2c_probe(EXPANSION_EEPROM_I2C_ADDRESS) == 1) {
215 i2c_set_bus_num(TWL4030_I2C_BUS);
216 return GUMSTIX_NO_EEPROM;
219 /* read configuration data */
220 i2c_read(EXPANSION_EEPROM_I2C_ADDRESS, 0, 1, (u8 *)&expansion_config,
221 sizeof(expansion_config));
223 i2c_set_bus_num(TWL4030_I2C_BUS);
225 return expansion_config.device_vendor;
229 * Routine: misc_init_r
230 * Description: Configure board specific parts
232 int misc_init_r(void)
234 twl4030_power_init();
235 twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON);
237 #if defined(CONFIG_CMD_NET)
241 printf("Board revision: %d\n", get_board_revision());
243 switch (get_sdio2_config()) {
245 puts("Tranceiver detected on mmc2\n");
246 MUX_OVERO_SDIO2_TRANSCEIVER();
249 puts("Direct connection on mmc2\n");
250 MUX_OVERO_SDIO2_DIRECT();
253 puts("Unable to detect mmc2 connection type\n");
256 switch (get_expansion_id()) {
258 printf("Recognized Summit expansion board (rev %d %s)\n",
259 expansion_config.revision,
260 expansion_config.fab_revision);
261 setenv("defaultdisplay", "dvi");
264 printf("Recognized Tobi expansion board (rev %d %s)\n",
265 expansion_config.revision,
266 expansion_config.fab_revision);
267 setenv("defaultdisplay", "dvi");
269 case GUMSTIX_TOBI_DUO:
270 printf("Recognized Tobi Duo expansion board (rev %d %s)\n",
271 expansion_config.revision,
272 expansion_config.fab_revision);
273 /* second lan chip */
274 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[4],
275 0x2B000000, GPMC_SIZE_16M);
278 printf("Recognized Palo35 expansion board (rev %d %s)\n",
279 expansion_config.revision,
280 expansion_config.fab_revision);
281 setenv("defaultdisplay", "lcd35");
284 printf("Recognized Palo43 expansion board (rev %d %s)\n",
285 expansion_config.revision,
286 expansion_config.fab_revision);
287 setenv("defaultdisplay", "lcd43");
289 case GUMSTIX_CHESTNUT43:
290 printf("Recognized Chestnut43 expansion board (rev %d %s)\n",
291 expansion_config.revision,
292 expansion_config.fab_revision);
293 setenv("defaultdisplay", "lcd43");
296 printf("Recognized Pinto expansion board (rev %d %s)\n",
297 expansion_config.revision,
298 expansion_config.fab_revision);
300 case GUMSTIX_GALLOP43:
301 printf("Recognized Gallop43 expansion board (rev %d %s)\n",
302 expansion_config.revision,
303 expansion_config.fab_revision);
304 setenv("defaultdisplay", "lcd43");
307 printf("Recognized Ettus Research USRP-E (rev %d %s)\n",
308 expansion_config.revision,
309 expansion_config.fab_revision);
311 setenv("defaultdisplay", "dvi");
313 case GUMSTIX_NO_EEPROM:
314 puts("No EEPROM on expansion board\n");
317 puts("Unrecognized expansion board\n");
320 if (expansion_config.content == 1)
321 setenv(expansion_config.env_var, expansion_config.env_setting);
329 * Routine: set_muxconf_regs
330 * Description: Setting up the configuration Mux registers specific to the
331 * hardware. Many pins need to be moved from protect to primary
334 void set_muxconf_regs(void)
339 #if defined(CONFIG_CMD_NET)
341 * Routine: setup_net_chip
342 * Description: Setting up the configuration GPMC registers specific to the
345 static void setup_net_chip(void)
347 struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
350 enable_gpmc_cs_config(gpmc_lan_config, &gpmc_cfg->cs[5], 0x2C000000,
353 /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
354 writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
355 /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
356 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
357 /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
358 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
359 &ctrl_base->gpmc_nadv_ale);
361 /* Make GPIO 64 as output pin and send a magic pulse through it */
362 if (!gpio_request(64, "")) {
363 gpio_direction_output(64, 0);
364 gpio_set_value(64, 1);
366 gpio_set_value(64, 0);
368 gpio_set_value(64, 1);
373 int board_eth_init(bd_t *bis)
376 #ifdef CONFIG_SMC911X
377 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
382 #if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
383 int board_mmc_init(bd_t *bis)
385 return omap_mmc_init(0, 0, 0, -1, -1);