3 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
5 * Eric Schumann, Phytec Messtechnik
6 * adapted for mt46v32m16-75 DDR-RAM
8 * SPDX-License-Identifier: GPL-2.0+
11 #define SDRAM_DDR 1 /* is DDR */
13 /* Settings for XLB = 132 MHz */
15 #define SDRAM_MODE 0x018D0000
16 #define SDRAM_EMODE 0x40090000
17 #define SDRAM_CONTROL 0x71500F00
18 #define SDRAM_CONFIG1 0x73711930
19 #define SDRAM_CONFIG2 0x47770000
21 #define SDRAM_TAPDELAY 0x10000000 /* reserved Bit in MPC5200 B3-Step */