3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
9 * Eric Schumann, Phytec Messtechnik GmbH
11 * SPDX-License-Identifier: GPL-2.0+
19 #include "mt46v32m16-75.h"
21 #ifndef CONFIG_SYS_RAMBOOT
22 static void sdram_start(int hi_addr)
24 volatile struct mpc5xxx_cdm *cdm =
25 (struct mpc5xxx_cdm *)MPC5XXX_CDM;
26 volatile struct mpc5xxx_sdram *sdram =
27 (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
29 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
31 /* unlock mode register */
32 out_be32 (&sdram->ctrl,
33 (SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
35 /* precharge all banks */
36 out_be32 (&sdram->ctrl,
37 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
40 /* set mode register: extended mode */
41 out_be32 (&sdram->mode, (SDRAM_EMODE));
43 /* set mode register: reset DLL */
44 out_be32 (&sdram->mode,
45 (SDRAM_MODE | 0x04000000));
48 /* precharge all banks */
49 out_be32 (&sdram->ctrl,
50 (SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
53 out_be32 (&sdram->ctrl,
54 (SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
56 /* set mode register */
57 out_be32 (&sdram->mode, (SDRAM_MODE));
59 /* normal operation */
60 out_be32 (&sdram->ctrl,
61 (SDRAM_CONTROL | hi_addr_bit));
63 /* set CDM clock enable register, set MPC5200B SDRAM bus */
64 /* to reduced driver strength */
65 out_be32 (&cdm->clock_enable, (0x00CFFFFF));
70 * ATTENTION: Although partially referenced initdram does NOT make
71 * real use of CONFIG_SYS_SDRAM_BASE. The code does not
72 * work if CONFIG_SYS_SDRAM_BASE
73 * is something else than 0x00000000.
76 phys_size_t initdram(int board_type)
78 volatile struct mpc5xxx_mmap_ctl *mm =
79 (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
80 volatile struct mpc5xxx_cdm *cdm =
81 (struct mpc5xxx_cdm *)MPC5XXX_CDM;
82 volatile struct mpc5xxx_sdram *sdram =
83 (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
86 #ifndef CONFIG_SYS_RAMBOOT
89 /* setup SDRAM chip selects */
91 out_be32 (&mm->sdram0, 0x0000001b);
93 out_be32 (&mm->sdram1, 0x10000000);
95 /* setup config registers */
96 out_be32 (&sdram->config1, SDRAM_CONFIG1);
97 out_be32 (&sdram->config2, SDRAM_CONFIG2);
99 #if defined(SDRAM_DDR) && defined(SDRAM_TAPDELAY)
101 out_be32 (&cdm->porcfg, SDRAM_TAPDELAY);
104 /* find RAM size using SDRAM CS0 only */
106 test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
108 test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
115 /* memory smaller than 1MB is impossible */
116 if (dramsize < (1 << 20))
119 /* set SDRAM CS0 size according to the amount of RAM found */
121 out_be32 (&mm->sdram0,
122 (0x13 + __builtin_ffs(dramsize >> 20) - 1));
125 out_be32 (&mm->sdram0, 0);
128 #else /* CONFIG_SYS_RAMBOOT */
130 /* retrieve size of memory connected to SDRAM CS0 */
131 dramsize = in_be32(&mm->sdram0) & 0xFF;
132 if (dramsize >= 0x13)
133 dramsize = (1 << (dramsize - 0x13)) << 20;
137 /* retrieve size of memory connected to SDRAM CS1 */
138 dramsize2 = in_be32(&mm->sdram1) & 0xFF;
139 if (dramsize2 >= 0x13)
140 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
144 #endif /* CONFIG_SYS_RAMBOOT */
146 return dramsize + dramsize2;
151 puts("Board: phyCORE-MPC5200B-tiny\n");
156 static struct pci_controller hose;
158 extern void pci_mpc5xxx_init(struct pci_controller *);
160 void pci_init_board(void)
162 pci_mpc5xxx_init(&hose);
166 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
167 void ft_board_setup(void *blob, bd_t * bd)
169 ft_cpu_setup(blob, bd);
171 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
173 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
175 #define GPIO_PSC2_4 0x02000000UL
177 void init_ide_reset(void)
179 volatile struct mpc5xxx_wu_gpio *wu_gpio =
180 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
181 debug("init_ide_reset\n");
183 /* Configure PSC2_4 as GPIO output for ATA reset */
184 setbits_be32(&wu_gpio->enable, GPIO_PSC2_4);
185 setbits_be32(&wu_gpio->ddr, GPIO_PSC2_4);
187 setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
190 void ide_set_reset(int idereset)
192 volatile struct mpc5xxx_wu_gpio *wu_gpio =
193 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
194 debug("ide_reset(%d)\n", idereset);
197 clrbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
198 /* Make a delay. MPC5200 spec says 25 usec min */
201 setbits_be32(&wu_gpio->dvo, GPIO_PSC2_4);
203 #endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */