4 * Board functions for Phytec phyCORE-AM335x (pcm051) based boards
6 * Copyright (C) 2013 Lemonage Software GmbH
7 * Author Lars Poeschel <poeschel@lemonage.de>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
17 * GNU General Public License for more details.
23 #include <asm/arch/cpu.h>
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/omap.h>
26 #include <asm/arch/ddr_defs.h>
27 #include <asm/arch/clock.h>
28 #include <asm/arch/gpio.h>
29 #include <asm/arch/mmc_host_def.h>
30 #include <asm/arch/sys_proto.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 static struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
42 #ifdef CONFIG_SPL_BUILD
43 static struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE;
46 /* MII mode defines */
47 #define MII_MODE_ENABLE 0x0
48 #define RGMII_MODE_ENABLE 0xA
49 #define RMII_RGMII2_MODE_ENABLE 0x49
51 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
54 #ifdef CONFIG_SPL_BUILD
55 #define UART_RESET (0x1 << 1)
56 #define UART_CLK_RUNNING_MASK 0x1
57 #define UART_SMART_IDLE_EN (0x1 << 0x3)
60 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
62 static void rtc32k_enable(void)
64 struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
67 * Unlock the RTC's registers. For more details please see the
68 * RTC_SS section of the TRM. In order to unlock we need to
69 * write these specific values (keys) in this order.
71 writel(0x83e70b13, &rtc->kick0r);
72 writel(0x95a4f1e0, &rtc->kick1r);
74 /* Enable the RTC 32K OSC by setting bits 3 and 6. */
75 writel((1 << 3) | (1 << 6), &rtc->osc);
78 static const struct ddr_data ddr3_data = {
79 .datardsratio0 = MT41J256M8HX15E_RD_DQS,
80 .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
81 .datafwsratio0 = MT41J256M8HX15E_PHY_FIFO_WE,
82 .datawrsratio0 = MT41J256M8HX15E_PHY_WR_DATA,
83 .datadldiff0 = PHY_DLL_LOCK_DIFF,
86 static const struct cmd_control ddr3_cmd_ctrl_data = {
87 .cmd0csratio = MT41J256M8HX15E_RATIO,
88 .cmd0dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
89 .cmd0iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
91 .cmd1csratio = MT41J256M8HX15E_RATIO,
92 .cmd1dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
93 .cmd1iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
95 .cmd2csratio = MT41J256M8HX15E_RATIO,
96 .cmd2dldiff = MT41J256M8HX15E_DLL_LOCK_DIFF,
97 .cmd2iclkout = MT41J256M8HX15E_INVERT_CLKOUT,
100 static struct emif_regs ddr3_emif_reg_data = {
101 .sdram_config = MT41J256M8HX15E_EMIF_SDCFG,
102 .ref_ctrl = MT41J256M8HX15E_EMIF_SDREF,
103 .sdram_tim1 = MT41J256M8HX15E_EMIF_TIM1,
104 .sdram_tim2 = MT41J256M8HX15E_EMIF_TIM2,
105 .sdram_tim3 = MT41J256M8HX15E_EMIF_TIM3,
106 .zq_config = MT41J256M8HX15E_ZQ_CFG,
107 .emif_ddr_phy_ctlr_1 = MT41J256M8HX15E_EMIF_READ_LATENCY |
113 * early system init of muxing and clocks.
118 * WDT1 is already running when the bootloader gets control
119 * Disable it to avoid "random" resets
121 writel(0xAAAA, &wdtimer->wdtwspr);
122 while (readl(&wdtimer->wdtwwps) != 0x0)
124 writel(0x5555, &wdtimer->wdtwspr);
125 while (readl(&wdtimer->wdtwwps) != 0x0)
128 #ifdef CONFIG_SPL_BUILD
129 /* Setup the PLLs and the clocks for the peripherals */
132 /* Enable RTC32K clock */
138 enable_uart0_pin_mux();
140 regval = readl(&uart_base->uartsyscfg);
141 regval |= UART_RESET;
142 writel(regval, &uart_base->uartsyscfg);
143 while ((readl(&uart_base->uartsyssts) & UART_CLK_RUNNING_MASK)
144 != UART_CLK_RUNNING_MASK)
147 /* Disable smart idle */
148 regval = readl(&uart_base->uartsyscfg);
149 regval |= UART_SMART_IDLE_EN;
150 writel(regval, &uart_base->uartsyscfg);
154 preloader_console_init();
156 /* Initalize the board header */
157 enable_i2c0_pin_mux();
158 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
160 enable_board_pin_mux();
162 config_ddr(DDR_CLK_MHZ, MT41J256M8HX15E_IOCTRL_VALUE, &ddr3_data,
163 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
168 * Basic board specific setup. Pinmux has been handled already.
172 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
174 gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
179 #ifdef CONFIG_DRIVER_TI_CPSW
180 static void cpsw_control(int enabled)
182 /* VTP can be added here */
187 static struct cpsw_slave_data cpsw_slaves[] = {
189 .slave_reg_ofs = 0x208,
190 .sliver_reg_ofs = 0xd80,
192 .phy_if = PHY_INTERFACE_MODE_RGMII,
195 .slave_reg_ofs = 0x308,
196 .sliver_reg_ofs = 0xdc0,
198 .phy_if = PHY_INTERFACE_MODE_RGMII,
202 static struct cpsw_platform_data cpsw_data = {
203 .mdio_base = CPSW_MDIO_BASE,
204 .cpsw_base = CPSW_BASE,
207 .cpdma_reg_ofs = 0x800,
209 .slave_data = cpsw_slaves,
210 .ale_reg_ofs = 0xd00,
212 .host_port_reg_ofs = 0x108,
213 .hw_stats_reg_ofs = 0x900,
214 .mac_control = (1 << 5),
215 .control = cpsw_control,
217 .version = CPSW_CTRL_VERSION_2,
221 #if defined(CONFIG_DRIVER_TI_CPSW) || \
222 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
223 int board_eth_init(bd_t *bis)
226 #ifdef CONFIG_DRIVER_TI_CPSW
228 uint32_t mac_hi, mac_lo;
230 if (!eth_getenv_enetaddr("ethaddr", mac_addr)) {
231 printf("<ethaddr> not set. Reading from E-fuse\n");
232 /* try reading mac address from efuse */
233 mac_lo = readl(&cdev->macid0l);
234 mac_hi = readl(&cdev->macid0h);
235 mac_addr[0] = mac_hi & 0xFF;
236 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
237 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
238 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
239 mac_addr[4] = mac_lo & 0xFF;
240 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
242 if (is_valid_ether_addr(mac_addr))
243 eth_setenv_enetaddr("ethaddr", mac_addr);
248 writel(RMII_RGMII2_MODE_ENABLE, &cdev->miisel);
250 rv = cpsw_register(&cpsw_data);
252 printf("Error %d registering CPSW switch\n", rv);
258 #if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD)
259 rv = usb_eth_initialize(bis);
261 printf("Error %d registering USB_ETHER\n", rv);