2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * SPDX-License-Identifier: GPL-2.0+
16 #if defined(CONFIG_MPC5200_DDR)
17 #include "mt46v16m16-75.h"
19 #include "mt48lc16m16a2-75.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 #ifndef CONFIG_SYS_RAMBOOT
25 static void sdram_start (int hi_addr)
27 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
29 /* unlock mode register */
30 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
31 __asm__ volatile ("sync");
33 /* precharge all banks */
34 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
35 __asm__ volatile ("sync");
38 /* set mode register: extended mode */
39 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
40 __asm__ volatile ("sync");
42 /* set mode register: reset DLL */
43 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
44 __asm__ volatile ("sync");
47 /* precharge all banks */
48 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
49 __asm__ volatile ("sync");
52 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
53 __asm__ volatile ("sync");
55 /* set mode register */
56 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
57 __asm__ volatile ("sync");
59 /* normal operation */
60 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
61 __asm__ volatile ("sync");
66 * ATTENTION: Although partially referenced initdram does NOT make real use
67 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
68 * is something else than 0x00000000.
71 phys_size_t initdram (int board_type)
75 #ifndef CONFIG_SYS_RAMBOOT
78 /* setup SDRAM chip selects */
79 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
80 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
81 __asm__ volatile ("sync");
83 /* setup config registers */
84 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
85 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
86 __asm__ volatile ("sync");
90 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
91 __asm__ volatile ("sync");
94 /* find RAM size using SDRAM CS0 only */
96 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
98 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
106 /* memory smaller than 1MB is impossible */
107 if (dramsize < (1 << 20)) {
111 /* set SDRAM CS0 size according to the amount of RAM found */
113 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
115 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
118 /* let SDRAM CS1 start right after CS0 */
119 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
121 /* find RAM size using SDRAM CS1 only */
124 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
127 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
136 /* memory smaller than 1MB is impossible */
137 if (dramsize2 < (1 << 20)) {
141 /* set SDRAM CS1 size according to the amount of RAM found */
143 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
144 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
146 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
149 #else /* CONFIG_SYS_RAMBOOT */
151 /* retrieve size of memory connected to SDRAM CS0 */
152 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
153 if (dramsize >= 0x13) {
154 dramsize = (1 << (dramsize - 0x13)) << 20;
159 /* retrieve size of memory connected to SDRAM CS1 */
160 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
161 if (dramsize2 >= 0x13) {
162 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
167 #endif /* CONFIG_SYS_RAMBOOT */
169 return dramsize + dramsize2;
172 int checkboard (void)
174 puts ("Board: MicroSys PM520 \n");
178 void flash_preinit(void)
181 * Now, when we are in RAM, enable flash write
182 * access for detection process.
183 * Note that CS_BOOT cannot be cleared when
184 * executing in flash.
186 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
189 void flash_afterinit(ulong start, ulong size)
191 #if defined(CONFIG_BOOT_ROM)
193 *(vu_long *)MPC5XXX_CS1_START =
195 *(vu_long *)MPC5XXX_CS1_STOP =
196 STOP_REG(start, size);
199 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
201 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
202 STOP_REG(start, size);
207 extern flash_info_t flash_info[]; /* info for FLASH chips */
209 int misc_init_r (void)
211 /* adjust flash start */
212 gd->bd->bi_flashstart = flash_info[0].start[0];
217 static struct pci_controller hose;
219 extern void pci_mpc5xxx_init(struct pci_controller *);
221 void pci_init_board(void)
223 pci_mpc5xxx_init(&hose);
227 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
229 void init_ide_reset (void)
231 debug ("init_ide_reset\n");
235 void ide_set_reset (int idereset)
237 debug ("ide_reset(%d)\n", idereset);
242 #if defined(CONFIG_CMD_DOC)
245 doc_probe (CONFIG_SYS_DOC_BASE);
249 int board_eth_init(bd_t *bis)
251 cpu_eth_init(bis); /* Built in FEC comes first */
252 return pci_eth_init(bis);