2 * (C) Copyright 2003-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 #if defined(CONFIG_MPC5200_DDR)
33 #include "mt46v16m16-75.h"
35 #include "mt48lc16m16a2-75.h"
38 DECLARE_GLOBAL_DATA_PTR;
40 #ifndef CONFIG_SYS_RAMBOOT
41 static void sdram_start (int hi_addr)
43 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
45 /* unlock mode register */
46 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
47 __asm__ volatile ("sync");
49 /* precharge all banks */
50 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
51 __asm__ volatile ("sync");
54 /* set mode register: extended mode */
55 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
56 __asm__ volatile ("sync");
58 /* set mode register: reset DLL */
59 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
60 __asm__ volatile ("sync");
63 /* precharge all banks */
64 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
65 __asm__ volatile ("sync");
68 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
69 __asm__ volatile ("sync");
71 /* set mode register */
72 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
73 __asm__ volatile ("sync");
75 /* normal operation */
76 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
77 __asm__ volatile ("sync");
82 * ATTENTION: Although partially referenced initdram does NOT make real use
83 * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
84 * is something else than 0x00000000.
87 phys_size_t initdram (int board_type)
91 #ifndef CONFIG_SYS_RAMBOOT
94 /* setup SDRAM chip selects */
95 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
96 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
97 __asm__ volatile ("sync");
99 /* setup config registers */
100 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
101 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
102 __asm__ volatile ("sync");
106 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
107 __asm__ volatile ("sync");
110 /* find RAM size using SDRAM CS0 only */
112 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
114 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
122 /* memory smaller than 1MB is impossible */
123 if (dramsize < (1 << 20)) {
127 /* set SDRAM CS0 size according to the amount of RAM found */
129 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
131 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
134 /* let SDRAM CS1 start right after CS0 */
135 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
137 /* find RAM size using SDRAM CS1 only */
140 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
143 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
152 /* memory smaller than 1MB is impossible */
153 if (dramsize2 < (1 << 20)) {
157 /* set SDRAM CS1 size according to the amount of RAM found */
159 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
160 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
162 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
165 #else /* CONFIG_SYS_RAMBOOT */
167 /* retrieve size of memory connected to SDRAM CS0 */
168 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
169 if (dramsize >= 0x13) {
170 dramsize = (1 << (dramsize - 0x13)) << 20;
175 /* retrieve size of memory connected to SDRAM CS1 */
176 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
177 if (dramsize2 >= 0x13) {
178 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
183 #endif /* CONFIG_SYS_RAMBOOT */
185 return dramsize + dramsize2;
188 int checkboard (void)
190 puts ("Board: MicroSys PM520 \n");
194 void flash_preinit(void)
197 * Now, when we are in RAM, enable flash write
198 * access for detection process.
199 * Note that CS_BOOT cannot be cleared when
200 * executing in flash.
202 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
205 void flash_afterinit(ulong start, ulong size)
207 #if defined(CONFIG_BOOT_ROM)
209 *(vu_long *)MPC5XXX_CS1_START =
211 *(vu_long *)MPC5XXX_CS1_STOP =
212 STOP_REG(start, size);
215 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
217 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
218 STOP_REG(start, size);
223 extern flash_info_t flash_info[]; /* info for FLASH chips */
225 int misc_init_r (void)
227 /* adjust flash start */
228 gd->bd->bi_flashstart = flash_info[0].start[0];
233 static struct pci_controller hose;
235 extern void pci_mpc5xxx_init(struct pci_controller *);
237 void pci_init_board(void)
239 pci_mpc5xxx_init(&hose);
243 #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
245 void init_ide_reset (void)
247 debug ("init_ide_reset\n");
251 void ide_set_reset (int idereset)
253 debug ("ide_reset(%d)\n", idereset);
258 #if defined(CONFIG_CMD_DOC)
261 doc_probe (CONFIG_SYS_DOC_BASE);
265 int board_eth_init(bd_t *bis)
267 cpu_eth_init(bis); /* Built in FEC comes first */
268 return pci_eth_init(bis);