4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/iomux-mx28.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
16 #include <linux/mii.h>
21 DECLARE_GLOBAL_DATA_PTR;
26 int board_early_init_f(void)
28 /* IO0 clock at 480MHz */
29 mxs_set_ioclk(MXC_IOCLK0, 480000);
30 /* IO1 clock at 480MHz */
31 mxs_set_ioclk(MXC_IOCLK1, 480000);
33 /* SSP2 clock at 160MHz */
34 mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
41 return mxs_dram_init();
46 /* Adress of boot parameters */
47 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
53 int board_eth_init(bd_t *bis)
55 struct mxs_clkctrl_regs *clkctrl_regs =
56 (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
57 struct eth_device *dev;
60 ret = cpu_eth_init(bis);
62 /* BG0900 uses ENET_CLK PAD to drive FEC clock */
63 writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
64 &clkctrl_regs->hw_clkctrl_enet);
67 gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
69 gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
71 ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
73 puts("FEC MXS: Unable to init FEC0\n");
77 dev = eth_get_dev_by_name("FEC0");
79 puts("FEC MXS: Unable to get FEC0 device entry\n");