3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <spd_sdram.h>
28 #include <ppc4xx_enet.h>
30 DECLARE_GLOBAL_DATA_PTR;
32 extern int alpr_fpga_init(void);
34 int board_early_init_f (void)
38 /*-------------------------------------------------------------------------+
39 | Initialize EBC CONFIG
40 +-------------------------------------------------------------------------*/
41 mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
42 EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
43 EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
44 EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
45 EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
47 /*--------------------------------------------------------------------
48 * Setup the interrupt controller polarities, triggers, etc.
49 *-------------------------------------------------------------------*/
50 mtdcr (uic0sr, 0xffffffff); /* clear all */
51 mtdcr (uic0er, 0x00000000); /* disable all */
52 mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
53 mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
54 mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
55 mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
56 mtdcr (uic0sr, 0xffffffff); /* clear all */
58 mtdcr (uic1sr, 0xffffffff); /* clear all */
59 mtdcr (uic1er, 0x00000000); /* disable all */
60 mtdcr (uic1cr, 0x00000000); /* all non-critical */
61 mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
62 mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
63 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
64 mtdcr (uic1sr, 0xffffffff); /* clear all */
66 mtdcr (uic2sr, 0xffffffff); /* clear all */
67 mtdcr (uic2er, 0x00000000); /* disable all */
68 mtdcr (uic2cr, 0x00000000); /* all non-critical */
69 mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
70 mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
71 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
72 mtdcr (uic2sr, 0xffffffff); /* clear all */
74 mtdcr (uicb0sr, 0xfc000000); /* clear all */
75 mtdcr (uicb0er, 0x00000000); /* disable all */
76 mtdcr (uicb0cr, 0x00000000); /* all non-critical */
77 mtdcr (uicb0pr, 0xfc000000); /* */
78 mtdcr (uicb0tr, 0x00000000); /* */
79 mtdcr (uicb0vr, 0x00000001); /* */
81 mfr &= ~SDR0_MFR_ECS_MASK;
88 char *s = getenv ("serial#");
90 printf ("Board: ALPR");
100 #if defined(CFG_DRAM_TEST)
103 uint *pstart = (uint *) 0x00000000;
104 uint *pend = (uint *) 0x08000000;
107 for (p = pstart; p < pend; p++)
110 for (p = pstart; p < pend; p++) {
111 if (*p != 0xaaaaaaaa) {
112 printf ("SDRAM test fails at: %08x\n", (uint) p);
117 for (p = pstart; p < pend; p++)
120 for (p = pstart; p < pend; p++) {
121 if (*p != 0x55555555) {
122 printf ("SDRAM test fails at: %08x\n", (uint) p);
130 /*************************************************************************
133 * This routine is called just prior to registering the hose and gives
134 * the board the opportunity to check things. Returning a value of zero
135 * indicates that things are bad & PCI initialization should be aborted.
137 * Different boards may wish to customize the pci controller structure
138 * (add regions, override default access routines, etc) or perform
139 * certain pre-initialization actions.
141 ************************************************************************/
142 #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
143 int pci_pre_init(struct pci_controller * hose )
147 /*--------------------------------------------------------------------------+
148 * The ocotea board is always configured as the host & requires the
149 * PCI arbiter to be enabled.
150 *--------------------------------------------------------------------------*/
151 mfsdr(sdr_sdstp1, strap);
152 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
153 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
162 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
164 /*************************************************************************
167 * The bootstrap configuration provides default settings for the pci
168 * inbound map (PIM). But the bootstrap config choices are limited and
169 * may not be sufficient for a given board.
171 ************************************************************************/
172 #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
173 void pci_target_init(struct pci_controller * hose )
175 /*--------------------------------------------------------------------------+
177 *--------------------------------------------------------------------------*/
178 out32r( PCIX0_PIM0SA, 0 ); /* disable */
179 out32r( PCIX0_PIM1SA, 0 ); /* disable */
180 out32r( PCIX0_PIM2SA, 0 ); /* disable */
181 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
183 /*--------------------------------------------------------------------------+
184 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
185 * options to not support sizes such as 128/256 MB.
186 *--------------------------------------------------------------------------*/
187 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
188 out32r( PCIX0_PIM0LAH, 0 );
189 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
191 out32r( PCIX0_BAR0, 0 );
193 /*--------------------------------------------------------------------------+
194 * Program the board's subsystem id/vendor id
195 *--------------------------------------------------------------------------*/
196 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
197 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
199 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
201 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
203 /*************************************************************************
206 * This routine is called to determine if a pci scan should be
207 * performed. With various hardware environments (especially cPCI and
208 * PPMC) it's insufficient to depend on the state of the arbiter enable
209 * bit in the strap register, or generic host/adapter assumptions.
211 * Rather than hard-code a bad assumption in the general 440 code, the
212 * 440 pci code requires the board to decide at runtime.
214 * Return 0 for adapter mode, non-zero for host (monarch) mode.
217 ************************************************************************/
218 #if defined(CONFIG_PCI)
219 int is_pci_host(struct pci_controller *hose)
221 /* The ocotea board is always configured as host. */
224 #endif /* defined(CONFIG_PCI) */
226 /*************************************************************************
229 ************************************************************************/
230 #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
231 void pci_master_init(struct pci_controller *hose)
233 unsigned short temp_short;
235 /*--------------------------------------------------------------------------+
236 | Write the PowerPC440 PCI Configuration regs.
237 | Enable PowerPC440 to be a master on the PCI bus (PMM).
238 | Enable PowerPC440 to act as a PCI memory target (PTM).
239 +--------------------------------------------------------------------------*/
240 pci_read_config_word(0, PCI_COMMAND, &temp_short);
241 pci_write_config_word(0, PCI_COMMAND,
242 temp_short | PCI_COMMAND_MASTER |
246 /*--------------------------------------------------------------------------+
247 | PowerPC440 PCI Master configuration.
248 | Map PLB/processor addresses to PCI memory space.
249 | PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
250 | Use byte reversed out routines to handle endianess.
251 | Make this region non-prefetchable.
252 +--------------------------------------------------------------------------*/
253 out32r( PCIX0_POM0SA, 0 ); /* disable */
254 out32r( PCIX0_POM1SA, 0 ); /* disable */
255 out32r( PCIX0_POM2SA, 0 ); /* disable */
257 out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */
258 out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */
259 out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
260 out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
261 out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
263 out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
264 out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */
265 out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
266 out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
267 out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */
271 #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
275 * Returns 1 if keys pressed to start the power-on long-running tests
276 * Called from board_init_f().
278 int post_hotkeys_pressed(void)