3 * Heiko Schocher, DENX Software Engineering, hs@denx.de
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * Altera FPGA configuration support for the ALPR computer from prodrive
33 #include <asm/processor.h>
34 #include <asm/ppc440.h>
37 DECLARE_GLOBAL_DATA_PTR;
39 #if defined(CONFIG_FPGA)
42 #define PRINTF(fmt, args...) printf(fmt , ##args)
44 #define PRINTF(fmt, args...)
47 static unsigned long regval;
49 #define SET_GPIO_REG_0(reg, bit) do { \
51 regval &= ~(0x80000000 >> bit); \
55 #define SET_GPIO_REG_1(reg, bit) do { \
57 regval |= (0x80000000 >> bit); \
61 #define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
62 #define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
64 #define FPGA_PRG (0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
65 #define FPGA_CONFIG (0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
66 #define FPGA_DATA (0x80000000 >> CONFIG_SYS_GPIO_DATA)
67 #define FPGA_CLK (0x80000000 >> CONFIG_SYS_GPIO_CLK)
68 #define OLD_VAL (FPGA_PRG | FPGA_CONFIG)
70 #define SET_FPGA(data) out32(GPIO0_OR, data)
72 #define FPGA_WRITE_1 do { \
73 SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \
74 SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA); /* set data to 1 */ \
77 #define FPGA_WRITE_0 do { \
78 SET_FPGA(OLD_VAL | 0 | 0); /* set data to 0 */ \
79 SET_FPGA(OLD_VAL | FPGA_CLK | 0); /* set data to 1 */ \
82 /* Plattforminitializations */
83 /* Here we have to set the FPGA Chain */
84 /* PROGRAM_PROG_EN = HIGH */
85 /* PROGRAM_SEL_DPR = LOW */
86 int fpga_pre_fn(int cookie)
88 /* Enable the FPGA Chain */
89 SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
90 SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
91 SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
92 SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
93 SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
94 SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));
96 /* initialize the GPIO Pins */
98 SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
99 SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
100 SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);
103 SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
104 SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
105 SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);
107 /* First we set STATUS to 0 then as an input */
108 SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
109 SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
110 SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
111 SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
112 SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
115 SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
116 SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
117 SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
120 SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
121 SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
122 SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);
124 /* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
125 SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
129 /* Set the state of CONFIG Pin */
130 int fpga_config_fn(int assert_config, int flush, int cookie)
133 SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
135 SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
140 /* Returns the state of STATUS Pin */
141 int fpga_status_fn(int cookie)
145 reg = in32(GPIO0_IR);
146 if (reg & (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
147 PRINTF("STATUS = HIGH\n");
150 PRINTF("STATUS = LOW\n");
154 /* Returns the state of CONF_DONE Pin */
155 int fpga_done_fn(int cookie)
158 reg = in32(GPIO0_IR);
159 if (reg & (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
160 PRINTF("CONF_DON = HIGH\n");
163 PRINTF("CONF_DON = LOW\n");
167 /* writes the complete buffer to the FPGA
168 writing the complete buffer in one function is much faster,
169 then calling it for every bit */
170 int fpga_write_fn(const void *buf, size_t len, int flush, int cookie)
172 size_t bytecount = 0;
173 unsigned char *data = (unsigned char *) buf;
174 unsigned char val = 0;
176 int len_40 = len / 40;
178 while (bytecount < len) {
179 val = data[bytecount++];
191 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
192 if (bytecount % len_40 == 0) {
193 putc('.'); /* let them know we are alive */
194 #ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
204 /* called, when programming is aborted */
205 int fpga_abort_fn(int cookie)
207 SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
211 /* called, when programming was succesful */
212 int fpga_post_fn(int cookie)
214 return fpga_abort_fn(cookie);
217 /* Note that these are pointers to code that is in Flash. They will be
218 * relocated at runtime.
220 Altera_CYC2_Passive_Serial_fns fpga_fns = {
230 Altera_desc fpga[CONFIG_FPGA_COUNT] = {
240 * Initialize the fpga. Return 1 on success, 0 on failure.
242 int alpr_fpga_init(void)
246 PRINTF("%s:%d: Initialize FPGA interface\n", __func__, __LINE__);
249 for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
250 PRINTF("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
251 fpga_add(fpga_altera, &fpga[i]);