3 * Heiko Schocher, DENX Software Engineering, hs@denx.de
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #if defined(CONFIG_CMD_NAND)
31 #include <asm/processor.h>
34 struct alpr_ndfc_regs {
44 static struct alpr_ndfc_regs *alpr_ndfc = NULL;
46 #define readb(addr) (u8)(*(volatile u8 *)(addr))
47 #define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
50 * The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
51 * the NAND devices. The NDFC has command, address and data registers that
52 * when accessed will set up the NAND flash pins appropriately. We'll use the
53 * hwcontrol function to save the configuration in a global variable.
54 * We can then use this information in the read and write functions to
55 * determine which NDFC register to access.
57 * There are 2 NAND devices on the board, a Hynix HY27US08561A (1 GByte).
59 static void alpr_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
61 struct nand_chip *this = mtd->priv;
63 if (ctrl & NAND_CTRL_CHANGE) {
64 if ( ctrl & NAND_CLE )
68 if ( ctrl & NAND_ALE )
72 if ( (ctrl & NAND_NCE) != NAND_NCE)
73 writeb(0x00, &(alpr_ndfc->term));
75 if (cmd != NAND_CMD_NONE)
76 writeb(cmd, this->IO_ADDR_W);
79 static u_char alpr_nand_read_byte(struct mtd_info *mtd)
81 return readb(&(alpr_ndfc->data));
84 static void alpr_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
86 struct nand_chip *nand = mtd->priv;
89 for (i = 0; i < len; i++) {
92 * IO_ADDR_W used as CMD[i] reg to support multiple NAND
95 writeb(buf[i], nand->IO_ADDR_W);
97 writeb(buf[i], &(alpr_ndfc->addr_wait));
99 writeb(buf[i], &(alpr_ndfc->data));
103 static void alpr_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
107 for (i = 0; i < len; i++) {
108 buf[i] = readb(&(alpr_ndfc->data));
112 static int alpr_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
116 for (i = 0; i < len; i++)
117 if (buf[i] != readb(&(alpr_ndfc->data)))
123 static int alpr_nand_dev_ready(struct mtd_info *mtd)
128 * Blocking read to wait for NAND to be ready
130 val = readb(&(alpr_ndfc->addr_wait));
138 int board_nand_init(struct nand_chip *nand)
140 alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
142 nand->ecc.mode = NAND_ECC_SOFT;
144 /* Reference hardware control function */
145 nand->cmd_ctrl = alpr_nand_hwcontrol;
146 nand->read_byte = alpr_nand_read_byte;
147 nand->write_buf = alpr_nand_write_buf;
148 nand->read_buf = alpr_nand_read_buf;
149 nand->verify_buf = alpr_nand_verify_buf;
150 nand->dev_ready = alpr_nand_dev_ready;