3 * Ingo Assmus <ingo.assmus@keymile.com>
5 * based on - Driver for MV64460X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * mv_eth.h - header file for the polled mode GT ethernet driver
31 #ifndef __DB64460_ETH_H__
32 #define __DB64460_ETH_H__
34 #include <asm/types.h>
36 #include <asm/byteorder.h>
40 #include <asm/errno.h>
41 #include "../../Marvell/include/core.h"
43 /*************************************************************************
44 **************************************************************************
45 **************************************************************************
46 * The first part is the high level driver of the gigE ethernet ports. *
47 **************************************************************************
48 **************************************************************************
49 *************************************************************************/
50 /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
52 #define MAX_SKB_FRAGS 0
56 /*#define MAX_RX_QUEUE_NUM 8*/
57 /*#define MAX_TX_QUEUE_NUM 8*/
58 #define MAX_RX_QUEUE_NUM 1
59 #define MAX_TX_QUEUE_NUM 1
62 /* Use one TX queue and one RX queue */
63 #define MV64460_TX_QUEUE_NUM 1
64 #define MV64460_RX_QUEUE_NUM 1
67 * Number of RX / TX descriptors on RX / TX rings.
68 * Note that allocating RX descriptors is done by allocating the RX
69 * ring AND a preallocated RX buffers (skb's) for each descriptor.
70 * The TX descriptors only allocates the TX descriptors ring,
71 * with no pre allocated TX buffers (skb's are allocated by higher layers.
74 /* Default TX ring size is 10 descriptors */
75 #ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
76 #define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
78 #define MV64460_TX_QUEUE_SIZE 4
81 /* Default RX ring size is 4 descriptors */
82 #ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE
83 #define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
85 #define MV64460_RX_QUEUE_SIZE 4
88 #ifdef CONFIG_RX_BUFFER_SIZE
89 #define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
91 #define MV64460_RX_BUFFER_SIZE 1600
94 #ifdef CONFIG_TX_BUFFER_SIZE
95 #define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
97 #define MV64460_TX_BUFFER_SIZE 1600
101 * Network device statistics. Akin to the 2.0 ether stats but
102 * with byte counters.
105 struct net_device_stats
107 unsigned long rx_packets; /* total packets received */
108 unsigned long tx_packets; /* total packets transmitted */
109 unsigned long rx_bytes; /* total bytes received */
110 unsigned long tx_bytes; /* total bytes transmitted */
111 unsigned long rx_errors; /* bad packets received */
112 unsigned long tx_errors; /* packet transmit problems */
113 unsigned long rx_dropped; /* no space in linux buffers */
114 unsigned long tx_dropped; /* no space available in linux */
115 unsigned long multicast; /* multicast packets received */
116 unsigned long collisions;
118 /* detailed rx_errors: */
119 unsigned long rx_length_errors;
120 unsigned long rx_over_errors; /* receiver ring buff overflow */
121 unsigned long rx_crc_errors; /* recved pkt with crc error */
122 unsigned long rx_frame_errors; /* recv'd frame alignment error */
123 unsigned long rx_fifo_errors; /* recv'r fifo overrun */
124 unsigned long rx_missed_errors; /* receiver missed packet */
126 /* detailed tx_errors */
127 unsigned long tx_aborted_errors;
128 unsigned long tx_carrier_errors;
129 unsigned long tx_fifo_errors;
130 unsigned long tx_heartbeat_errors;
131 unsigned long tx_window_errors;
134 unsigned long rx_compressed;
135 unsigned long tx_compressed;
139 /* Private data structure used for ethernet device */
140 struct mv64460_eth_priv {
141 unsigned int port_num;
142 struct net_device_stats *stats;
144 /* to buffer area aligned */
145 char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
146 char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
148 /* Size of Tx Ring per queue */
149 unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
151 /* Size of Rx Ring per queue */
152 unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
154 /* Magic Number for Ethernet running */
155 unsigned int eth_running;
160 int mv64460_eth_init (struct eth_device *dev);
161 int mv64460_eth_stop (struct eth_device *dev);
162 int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length);
163 int mv64460_eth_open (struct eth_device *dev);
166 /*************************************************************************
167 **************************************************************************
168 **************************************************************************
169 * The second part is the low level driver of the gigE ethernet ports. *
170 **************************************************************************
171 **************************************************************************
172 *************************************************************************/
175 /********************************************************************************
176 * Header File for : MV-643xx network interface header
179 * This header file contains macros typedefs and function declaration for
180 * the Marvell Gig Bit Ethernet Controller.
185 *******************************************************************************/
188 #ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
189 #ifdef CONFIG_MV64460_SRAM_CACHEABLE
190 /* In case SRAM is cacheable but not cache coherent */
191 #define D_CACHE_FLUSH_LINE(addr, offset) \
193 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
196 /* In case SRAM is cache coherent or non-cacheable */
197 #define D_CACHE_FLUSH_LINE(addr, offset) ;
200 #ifdef CONFIG_NOT_COHERENT_CACHE
201 /* In case of descriptors on DDR but not cache coherent */
202 #define D_CACHE_FLUSH_LINE(addr, offset) \
204 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
207 /* In case of descriptors on DDR and cache coherent */
208 #define D_CACHE_FLUSH_LINE(addr, offset) ;
209 #endif /* CONFIG_NOT_COHERENT_CACHE */
210 #endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
213 #define CPU_PIPE_FLUSH \
215 __asm__ __volatile__ ("eieio"); \
221 /* Default port configuration value */
222 #define PORT_CONFIG_VALUE \
223 ETH_UNICAST_NORMAL_MODE | \
224 ETH_DEFAULT_RX_QUEUE_0 | \
225 ETH_DEFAULT_RX_ARP_QUEUE_0 | \
226 ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
227 ETH_RECEIVE_BC_IF_IP | \
228 ETH_RECEIVE_BC_IF_ARP | \
229 ETH_CAPTURE_TCP_FRAMES_DIS | \
230 ETH_CAPTURE_UDP_FRAMES_DIS | \
231 ETH_DEFAULT_RX_TCP_QUEUE_0 | \
232 ETH_DEFAULT_RX_UDP_QUEUE_0 | \
233 ETH_DEFAULT_RX_BPDU_QUEUE_0
235 /* Default port extend configuration value */
236 #define PORT_CONFIG_EXTEND_VALUE \
237 ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
238 ETH_PARTITION_DISABLE
241 /* Default sdma control value */
242 #ifdef CONFIG_NOT_COHERENT_CACHE
243 #define PORT_SDMA_CONFIG_VALUE \
244 ETH_RX_BURST_SIZE_16_64BIT | \
245 GT_ETH_IPG_INT_RX(0) | \
246 ETH_TX_BURST_SIZE_16_64BIT;
248 #define PORT_SDMA_CONFIG_VALUE \
249 ETH_RX_BURST_SIZE_4_64BIT | \
250 GT_ETH_IPG_INT_RX(0) | \
251 ETH_TX_BURST_SIZE_4_64BIT;
254 #define GT_ETH_IPG_INT_RX(value) \
255 ((value & 0x3fff) << 8)
257 /* Default port serial control value */
258 #define PORT_SERIAL_CONTROL_VALUE \
259 ETH_FORCE_LINK_PASS | \
260 ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
261 ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
262 ETH_ADV_SYMMETRIC_FLOW_CTRL | \
263 ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
264 ETH_FORCE_BP_MODE_NO_JAM | \
266 ETH_DO_NOT_FORCE_LINK_FAIL | \
267 ETH_RETRANSMIT_16_ETTEMPTS | \
268 ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
270 ETH_DISABLE_AUTO_NEG_BYPASS | \
271 ETH_AUTO_NEG_NO_CHANGE | \
272 ETH_MAX_RX_PACKET_1552BYTE | \
273 ETH_CLR_EXT_LOOPBACK | \
274 ETH_SET_FULL_DUPLEX_MODE | \
275 ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
277 #define RX_BUFFER_MAX_SIZE 0xFFFF
278 #define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
280 #define RX_BUFFER_MIN_SIZE 0x8
281 #define TX_BUFFER_MIN_SIZE 0x8
283 /* Tx WRR confoguration macros */
284 #define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
285 #define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
286 #define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
288 /* MAC accepet/reject macros */
289 #define ACCEPT_MAC_ADDR 0
290 #define REJECT_MAC_ADDR 1
292 /* Size of a Tx/Rx descriptor used in chain list data structure */
293 #define RX_DESC_ALIGNED_SIZE 0x20
294 #define TX_DESC_ALIGNED_SIZE 0x20
296 /* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
297 #define TX_BUF_OFFSET_IN_DESC 0x18
298 /* Buffer offset from buffer pointer */
299 #define RX_BUF_OFFSET 0x2
302 #define ETH_BAR_GAP 0x8
303 #define ETH_SIZE_REG_GAP 0x8
304 #define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
305 #define ETH_PORT_ACCESS_CTRL_GAP 0x4
307 /* Gigabit Ethernet Unit Global Registers */
309 /* MIB Counters register definitions */
310 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
311 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
312 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
313 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
314 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
315 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
316 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
317 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
318 #define ETH_MIB_FRAMES_64_OCTETS 0x20
319 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
320 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
321 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
322 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
323 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
324 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
325 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
326 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
327 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
328 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
329 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
330 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
331 #define ETH_MIB_FC_SENT 0x54
332 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
333 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
334 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
335 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
336 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
337 #define ETH_MIB_JABBER_RECEIVED 0x6c
338 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
339 #define ETH_MIB_BAD_CRC_EVENT 0x74
340 #define ETH_MIB_COLLISION 0x78
341 #define ETH_MIB_LATE_COLLISION 0x7c
343 /* Port serial status reg (PSR) */
344 #define ETH_INTERFACE_GMII_MII 0
345 #define ETH_INTERFACE_PCM BIT0
346 #define ETH_LINK_IS_DOWN 0
347 #define ETH_LINK_IS_UP BIT1
348 #define ETH_PORT_AT_HALF_DUPLEX 0
349 #define ETH_PORT_AT_FULL_DUPLEX BIT2
350 #define ETH_RX_FLOW_CTRL_DISABLED 0
351 #define ETH_RX_FLOW_CTRL_ENBALED BIT3
352 #define ETH_GMII_SPEED_100_10 0
353 #define ETH_GMII_SPEED_1000 BIT4
354 #define ETH_MII_SPEED_10 0
355 #define ETH_MII_SPEED_100 BIT5
357 #define ETH_TX_IN_PROGRESS BIT7
358 #define ETH_BYPASS_NO_ACTIVE 0
359 #define ETH_BYPASS_ACTIVE BIT8
360 #define ETH_PORT_NOT_AT_PARTITION_STATE 0
361 #define ETH_PORT_AT_PARTITION_STATE BIT9
362 #define ETH_PORT_TX_FIFO_NOT_EMPTY 0
363 #define ETH_PORT_TX_FIFO_EMPTY BIT10
366 /* These macros describes the Port configuration reg (Px_cR) bits */
367 #define ETH_UNICAST_NORMAL_MODE 0
368 #define ETH_UNICAST_PROMISCUOUS_MODE BIT0
369 #define ETH_DEFAULT_RX_QUEUE_0 0
370 #define ETH_DEFAULT_RX_QUEUE_1 BIT1
371 #define ETH_DEFAULT_RX_QUEUE_2 BIT2
372 #define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
373 #define ETH_DEFAULT_RX_QUEUE_4 BIT3
374 #define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
375 #define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
376 #define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
377 #define ETH_DEFAULT_RX_ARP_QUEUE_0 0
378 #define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
379 #define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
380 #define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
381 #define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
382 #define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
383 #define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
384 #define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
385 #define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
386 #define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
387 #define ETH_RECEIVE_BC_IF_IP 0
388 #define ETH_REJECT_BC_IF_IP BIT8
389 #define ETH_RECEIVE_BC_IF_ARP 0
390 #define ETH_REJECT_BC_IF_ARP BIT9
391 #define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
392 #define ETH_CAPTURE_TCP_FRAMES_DIS 0
393 #define ETH_CAPTURE_TCP_FRAMES_EN BIT14
394 #define ETH_CAPTURE_UDP_FRAMES_DIS 0
395 #define ETH_CAPTURE_UDP_FRAMES_EN BIT15
396 #define ETH_DEFAULT_RX_TCP_QUEUE_0 0
397 #define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
398 #define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
399 #define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
400 #define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
401 #define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
402 #define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
403 #define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
404 #define ETH_DEFAULT_RX_UDP_QUEUE_0 0
405 #define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
406 #define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
407 #define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
408 #define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
409 #define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
410 #define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
411 #define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
412 #define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
413 #define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
414 #define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
415 #define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
416 #define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
417 #define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
418 #define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
419 #define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
422 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
423 #define ETH_CLASSIFY_EN BIT0
424 #define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
425 #define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
426 #define ETH_PARTITION_DISABLE 0
427 #define ETH_PARTITION_ENABLE BIT2
430 /* Tx/Rx queue command reg (RQCR/TQCR)*/
431 #define ETH_QUEUE_0_ENABLE BIT0
432 #define ETH_QUEUE_1_ENABLE BIT1
433 #define ETH_QUEUE_2_ENABLE BIT2
434 #define ETH_QUEUE_3_ENABLE BIT3
435 #define ETH_QUEUE_4_ENABLE BIT4
436 #define ETH_QUEUE_5_ENABLE BIT5
437 #define ETH_QUEUE_6_ENABLE BIT6
438 #define ETH_QUEUE_7_ENABLE BIT7
439 #define ETH_QUEUE_0_DISABLE BIT8
440 #define ETH_QUEUE_1_DISABLE BIT9
441 #define ETH_QUEUE_2_DISABLE BIT10
442 #define ETH_QUEUE_3_DISABLE BIT11
443 #define ETH_QUEUE_4_DISABLE BIT12
444 #define ETH_QUEUE_5_DISABLE BIT13
445 #define ETH_QUEUE_6_DISABLE BIT14
446 #define ETH_QUEUE_7_DISABLE BIT15
448 /* These macros describes the Port Sdma configuration reg (SDCR) bits */
449 #define ETH_RIFB BIT0
450 #define ETH_RX_BURST_SIZE_1_64BIT 0
451 #define ETH_RX_BURST_SIZE_2_64BIT BIT1
452 #define ETH_RX_BURST_SIZE_4_64BIT BIT2
453 #define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
454 #define ETH_RX_BURST_SIZE_16_64BIT BIT3
455 #define ETH_BLM_RX_NO_SWAP BIT4
456 #define ETH_BLM_RX_BYTE_SWAP 0
457 #define ETH_BLM_TX_NO_SWAP BIT5
458 #define ETH_BLM_TX_BYTE_SWAP 0
459 #define ETH_DESCRIPTORS_BYTE_SWAP BIT6
460 #define ETH_DESCRIPTORS_NO_SWAP 0
461 #define ETH_TX_BURST_SIZE_1_64BIT 0
462 #define ETH_TX_BURST_SIZE_2_64BIT BIT22
463 #define ETH_TX_BURST_SIZE_4_64BIT BIT23
464 #define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
465 #define ETH_TX_BURST_SIZE_16_64BIT BIT24
467 /* These macros describes the Port serial control reg (PSCR) bits */
468 #define ETH_SERIAL_PORT_DISABLE 0
469 #define ETH_SERIAL_PORT_ENABLE BIT0
470 #define ETH_FORCE_LINK_PASS BIT1
471 #define ETH_DO_NOT_FORCE_LINK_PASS 0
472 #define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
473 #define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
474 #define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
475 #define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
476 #define ETH_ADV_NO_FLOW_CTRL 0
477 #define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
478 #define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
479 #define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
480 #define ETH_FORCE_BP_MODE_NO_JAM 0
481 #define ETH_FORCE_BP_MODE_JAM_TX BIT7
482 #define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
483 #define ETH_FORCE_LINK_FAIL 0
484 #define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
485 #define ETH_RETRANSMIT_16_ETTEMPTS 0
486 #define ETH_RETRANSMIT_FOREVER BIT11
487 #define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
488 #define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
489 #define ETH_DTE_ADV_0 0
490 #define ETH_DTE_ADV_1 BIT14
491 #define ETH_DISABLE_AUTO_NEG_BYPASS 0
492 #define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
493 #define ETH_AUTO_NEG_NO_CHANGE 0
494 #define ETH_RESTART_AUTO_NEG BIT16
495 #define ETH_MAX_RX_PACKET_1518BYTE 0
496 #define ETH_MAX_RX_PACKET_1522BYTE BIT17
497 #define ETH_MAX_RX_PACKET_1552BYTE BIT18
498 #define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
499 #define ETH_MAX_RX_PACKET_9192BYTE BIT19
500 #define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
501 #define ETH_SET_EXT_LOOPBACK BIT20
502 #define ETH_CLR_EXT_LOOPBACK 0
503 #define ETH_SET_FULL_DUPLEX_MODE BIT21
504 #define ETH_SET_HALF_DUPLEX_MODE 0
505 #define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
506 #define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
507 #define ETH_SET_GMII_SPEED_TO_10_100 0
508 #define ETH_SET_GMII_SPEED_TO_1000 BIT23
509 #define ETH_SET_MII_SPEED_TO_10 0
510 #define ETH_SET_MII_SPEED_TO_100 BIT24
514 #define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
515 #define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
516 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
517 #define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
519 /* SDMA command status fields macros */
521 /* Tx & Rx descriptors status */
522 #define ETH_ERROR_SUMMARY (BIT0)
524 /* Tx & Rx descriptors command */
525 #define ETH_BUFFER_OWNED_BY_DMA (BIT31)
527 /* Tx descriptors status */
528 #define ETH_LC_ERROR (0 )
529 #define ETH_UR_ERROR (BIT1 )
530 #define ETH_RL_ERROR (BIT2 )
531 #define ETH_LLC_SNAP_FORMAT (BIT9 )
533 /* Rx descriptors status */
534 #define ETH_CRC_ERROR (0 )
535 #define ETH_OVERRUN_ERROR (BIT1 )
536 #define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
537 #define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
538 #define ETH_VLAN_TAGGED (BIT19)
539 #define ETH_BPDU_FRAME (BIT20)
540 #define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
541 #define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
542 #define ETH_OTHER_FRAME_TYPE (BIT22)
543 #define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
544 #define ETH_FRAME_TYPE_IP_V_4 (BIT24)
545 #define ETH_FRAME_HEADER_OK (BIT25)
546 #define ETH_RX_LAST_DESC (BIT26)
547 #define ETH_RX_FIRST_DESC (BIT27)
548 #define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
549 #define ETH_RX_ENABLE_INTERRUPT (BIT29)
550 #define ETH_LAYER_4_CHECKSUM_OK (BIT30)
552 /* Rx descriptors byte count */
553 #define ETH_FRAME_FRAGMENTED (BIT2)
555 /* Tx descriptors command */
556 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
557 #define ETH_FRAME_SET_TO_VLAN (BIT15)
558 #define ETH_TCP_FRAME (0 )
559 #define ETH_UDP_FRAME (BIT16)
560 #define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
561 #define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
562 #define ETH_ZERO_PADDING (BIT19)
563 #define ETH_TX_LAST_DESC (BIT20)
564 #define ETH_TX_FIRST_DESC (BIT21)
565 #define ETH_GEN_CRC (BIT22)
566 #define ETH_TX_ENABLE_INTERRUPT (BIT23)
567 #define ETH_AUTO_MODE (BIT30)
569 /* Address decode parameters */
570 /* Ethernet Base Address Register bits */
571 #define EBAR_TARGET_DRAM 0x00000000
572 #define EBAR_TARGET_DEVICE 0x00000001
573 #define EBAR_TARGET_CBS 0x00000002
574 #define EBAR_TARGET_PCI0 0x00000003
575 #define EBAR_TARGET_PCI1 0x00000004
576 #define EBAR_TARGET_CUNIT 0x00000005
577 #define EBAR_TARGET_AUNIT 0x00000006
578 #define EBAR_TARGET_GUNIT 0x00000007
580 /* Window attributes */
581 #define EBAR_ATTR_DRAM_CS0 0x00000E00
582 #define EBAR_ATTR_DRAM_CS1 0x00000D00
583 #define EBAR_ATTR_DRAM_CS2 0x00000B00
584 #define EBAR_ATTR_DRAM_CS3 0x00000700
586 /* DRAM Target interface */
587 #define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
588 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
589 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
591 /* Device Bus Target interface */
592 #define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
593 #define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
594 #define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
595 #define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
596 #define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
598 /* PCI Target interface */
599 #define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
600 #define EBAR_ATTR_PCI_NO_SWAP 0x00000100
601 #define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
602 #define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
603 #define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
604 #define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
605 #define EBAR_ATTR_PCI_IO_SPACE 0x00000000
606 #define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
607 #define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
608 #define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
610 /* CPU 60x bus or internal SRAM interface */
611 #define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
612 #define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
613 #define EBAR_ATTR_CBS_SRAM 0x00000000
614 #define EBAR_ATTR_CBS_CPU_BUS 0x00000800
616 /* Window access control */
617 #define EWIN_ACCESS_NOT_ALLOWED 0
618 #define EWIN_ACCESS_READ_ONLY BIT0
619 #define EWIN_ACCESS_FULL (BIT1 | BIT0)
620 #define EWIN0_ACCESS_MASK 0x0003
621 #define EWIN1_ACCESS_MASK 0x000C
622 #define EWIN2_ACCESS_MASK 0x0030
623 #define EWIN3_ACCESS_MASK 0x00C0
627 typedef enum _eth_port
634 typedef enum _eth_func_ret_status
636 ETH_OK, /* Returned as expected. */
637 ETH_ERROR, /* Fundamental error. */
638 ETH_RETRY, /* Could not process request. Try later. */
639 ETH_END_OF_JOB, /* Ring has nothing to process. */
640 ETH_QUEUE_FULL, /* Ring resource error. */
641 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
642 }ETH_FUNC_RET_STATUS;
644 typedef enum _eth_queue
656 typedef enum _addr_win
666 typedef enum _eth_target
675 typedef struct _eth_rx_desc
677 unsigned short byte_cnt ; /* Descriptor buffer byte count */
678 unsigned short buf_size ; /* Buffer size */
679 unsigned int cmd_sts ; /* Descriptor command status */
680 unsigned int next_desc_ptr; /* Next descriptor pointer */
681 unsigned int buf_ptr ; /* Descriptor buffer pointer */
682 unsigned int return_info ; /* User resource return information */
686 typedef struct _eth_tx_desc
688 unsigned short byte_cnt ; /* Descriptor buffer byte count */
689 unsigned short l4i_chk ; /* CPU provided TCP Checksum */
690 unsigned int cmd_sts ; /* Descriptor command status */
691 unsigned int next_desc_ptr; /* Next descriptor pointer */
692 unsigned int buf_ptr ; /* Descriptor buffer pointer */
693 unsigned int return_info ; /* User resource return information */
696 /* Unified struct for Rx and Tx operations. The user is not required to */
697 /* be familier with neither Tx nor Rx descriptors. */
698 typedef struct _pkt_info
700 unsigned short byte_cnt ; /* Descriptor buffer byte count */
701 unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
702 unsigned int cmd_sts ; /* Descriptor command status */
703 unsigned int buf_ptr ; /* Descriptor buffer pointer */
704 unsigned int return_info ; /* User resource return information */
708 typedef struct _eth_win_param
710 ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
711 ETH_TARGET target; /* System targets. See ETH_TARGET enum */
712 unsigned short attributes; /* BAR attributes. See above macros. */
713 unsigned int base_addr; /* Window base address in unsigned int form */
714 unsigned int high_addr; /* Window high address in unsigned int form */
715 unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
716 bool enable; /* Enable/disable access to the window. */
717 unsigned short access_ctrl; /* Access ctrl register. see above macros */
721 /* Ethernet port specific infomation */
723 typedef struct _eth_port_ctrl
725 ETH_PORT port_num; /* User Ethernet port number */
726 int port_phy_addr; /* User phy address of Ethrnet port */
727 unsigned char port_mac_addr[6]; /* User defined port MAC address. */
728 unsigned int port_config; /* User port configuration value */
729 unsigned int port_config_extend; /* User port config extend value */
730 unsigned int port_sdma_config; /* User port SDMA config value */
731 unsigned int port_serial_control; /* User port serial control value */
732 unsigned int port_tx_queue_command; /* Port active Tx queues summary */
733 unsigned int port_rx_queue_command; /* Port active Rx queues summary */
735 /* User function to cast virtual address to CPU bus address */
736 unsigned int (*port_virt_to_phys)(unsigned int addr);
737 /* User scratch pad for user specific data structures */
740 bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
741 bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
743 /* Tx/Rx rings managment indexes fields. For driver use */
745 /* Next available Rx resource */
746 volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
747 /* Returning Rx resource */
748 volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
750 /* Next available Tx resource */
751 volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
752 /* Returning Tx resource */
753 volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
754 /* An extra Tx index to support transmit of multiple buffers per packet */
755 volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
757 /* Tx/Rx rings size and base variables fields. For driver use */
759 volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
760 unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
761 char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
763 volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
764 unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
765 char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
770 /* ethernet.h API list */
772 /* Port operation control routines */
773 static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
774 static void eth_port_reset(ETH_PORT eth_port_num);
775 static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
778 /* Port MAC address routines */
779 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
780 unsigned char *p_addr,
783 static void eth_port_mc_addr (ETH_PORT eth_port_num,
784 unsigned char *p_addr,
789 /* PHY and MIB routines */
790 static bool ethernet_phy_reset(ETH_PORT eth_port_num);
792 static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
793 unsigned int phy_reg,
796 static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
797 unsigned int phy_reg,
798 unsigned int* value);
800 static void eth_clear_mib_counters(ETH_PORT eth_port_num);
802 /* Port data flow control routines */
803 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
805 PKT_INFO *p_pkt_info);
806 static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
808 PKT_INFO *p_pkt_info);
809 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
811 PKT_INFO *p_pkt_info);
812 static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
814 PKT_INFO *p_pkt_info);
817 static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
821 unsigned int tx_desc_base_addr,
822 unsigned int tx_buff_base_addr);
824 static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
828 unsigned int rx_desc_base_addr,
829 unsigned int rx_buff_base_addr);
831 #endif /* MV64460_ETH_ */