3 * Ingo Assmus <ingo.assmus@keymile.com>
5 * based on - Driver for MV64460X ethernet ports
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * SPDX-License-Identifier: GPL-2.0+
12 * mv_eth.h - header file for the polled mode GT ethernet driver
15 #ifndef __DB64460_ETH_H__
16 #define __DB64460_ETH_H__
18 #include <asm/types.h>
20 #include <asm/byteorder.h>
24 #include <asm/errno.h>
25 #include "../../Marvell/include/core.h"
27 /*************************************************************************
28 **************************************************************************
29 **************************************************************************
30 * The first part is the high level driver of the gigE ethernet ports. *
31 **************************************************************************
32 **************************************************************************
33 *************************************************************************/
34 /* In case not using SG on Tx, define MAX_SKB_FRAGS as 0 */
36 #define MAX_SKB_FRAGS 0
40 /*#define MAX_RX_QUEUE_NUM 8*/
41 /*#define MAX_TX_QUEUE_NUM 8*/
42 #define MAX_RX_QUEUE_NUM 1
43 #define MAX_TX_QUEUE_NUM 1
46 /* Use one TX queue and one RX queue */
47 #define MV64460_TX_QUEUE_NUM 1
48 #define MV64460_RX_QUEUE_NUM 1
51 * Number of RX / TX descriptors on RX / TX rings.
52 * Note that allocating RX descriptors is done by allocating the RX
53 * ring AND a preallocated RX buffers (skb's) for each descriptor.
54 * The TX descriptors only allocates the TX descriptors ring,
55 * with no pre allocated TX buffers (skb's are allocated by higher layers.
58 /* Default TX ring size is 10 descriptors */
59 #ifdef CONFIG_MV64460_ETH_TXQUEUE_SIZE
60 #define MV64460_TX_QUEUE_SIZE CONFIG_MV64460_ETH_TXQUEUE_SIZE
62 #define MV64460_TX_QUEUE_SIZE 4
65 /* Default RX ring size is 4 descriptors */
66 #ifdef CONFIG_MV64460_ETH_RXQUEUE_SIZE
67 #define MV64460_RX_QUEUE_SIZE CONFIG_MV64460_ETH_RXQUEUE_SIZE
69 #define MV64460_RX_QUEUE_SIZE 4
72 #ifdef CONFIG_RX_BUFFER_SIZE
73 #define MV64460_RX_BUFFER_SIZE CONFIG_RX_BUFFER_SIZE
75 #define MV64460_RX_BUFFER_SIZE 1600
78 #ifdef CONFIG_TX_BUFFER_SIZE
79 #define MV64460_TX_BUFFER_SIZE CONFIG_TX_BUFFER_SIZE
81 #define MV64460_TX_BUFFER_SIZE 1600
85 * Network device statistics. Akin to the 2.0 ether stats but
89 struct net_device_stats
91 unsigned long rx_packets; /* total packets received */
92 unsigned long tx_packets; /* total packets transmitted */
93 unsigned long rx_bytes; /* total bytes received */
94 unsigned long tx_bytes; /* total bytes transmitted */
95 unsigned long rx_errors; /* bad packets received */
96 unsigned long tx_errors; /* packet transmit problems */
97 unsigned long rx_dropped; /* no space in linux buffers */
98 unsigned long tx_dropped; /* no space available in linux */
99 unsigned long multicast; /* multicast packets received */
100 unsigned long collisions;
102 /* detailed rx_errors: */
103 unsigned long rx_length_errors;
104 unsigned long rx_over_errors; /* receiver ring buff overflow */
105 unsigned long rx_crc_errors; /* recved pkt with crc error */
106 unsigned long rx_frame_errors; /* recv'd frame alignment error */
107 unsigned long rx_fifo_errors; /* recv'r fifo overrun */
108 unsigned long rx_missed_errors; /* receiver missed packet */
110 /* detailed tx_errors */
111 unsigned long tx_aborted_errors;
112 unsigned long tx_carrier_errors;
113 unsigned long tx_fifo_errors;
114 unsigned long tx_heartbeat_errors;
115 unsigned long tx_window_errors;
118 unsigned long rx_compressed;
119 unsigned long tx_compressed;
123 /* Private data structure used for ethernet device */
124 struct mv64460_eth_priv {
125 unsigned int port_num;
126 struct net_device_stats *stats;
128 /* to buffer area aligned */
129 char * p_eth_tx_buffer[MV64460_TX_QUEUE_SIZE+1]; /*pointers to alligned tx buffs in memory space */
130 char * p_eth_rx_buffer[MV64460_RX_QUEUE_SIZE+1]; /*pointers to allinged rx buffs in memory space */
132 /* Size of Tx Ring per queue */
133 unsigned int tx_ring_size [MAX_TX_QUEUE_NUM];
135 /* Size of Rx Ring per queue */
136 unsigned int rx_ring_size [MAX_RX_QUEUE_NUM];
138 /* Magic Number for Ethernet running */
139 unsigned int eth_running;
144 int mv64460_eth_init (struct eth_device *dev);
145 int mv64460_eth_stop (struct eth_device *dev);
146 int mv64460_eth_start_xmit(struct eth_device *dev, void *packet, int length);
147 int mv64460_eth_open (struct eth_device *dev);
150 /*************************************************************************
151 **************************************************************************
152 **************************************************************************
153 * The second part is the low level driver of the gigE ethernet ports. *
154 **************************************************************************
155 **************************************************************************
156 *************************************************************************/
159 /********************************************************************************
160 * Header File for : MV-643xx network interface header
163 * This header file contains macros typedefs and function declaration for
164 * the Marvell Gig Bit Ethernet Controller.
169 *******************************************************************************/
172 #ifdef CONFIG_SPECIAL_CONSISTENT_MEMORY
173 #ifdef CONFIG_MV64460_SRAM_CACHEABLE
174 /* In case SRAM is cacheable but not cache coherent */
175 #define D_CACHE_FLUSH_LINE(addr, offset) \
177 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
180 /* In case SRAM is cache coherent or non-cacheable */
181 #define D_CACHE_FLUSH_LINE(addr, offset) ;
184 #ifdef CONFIG_NOT_COHERENT_CACHE
185 /* In case of descriptors on DDR but not cache coherent */
186 #define D_CACHE_FLUSH_LINE(addr, offset) \
188 __asm__ __volatile__ ("dcbf %0,%1" : : "r" (addr), "r" (offset)); \
191 /* In case of descriptors on DDR and cache coherent */
192 #define D_CACHE_FLUSH_LINE(addr, offset) ;
193 #endif /* CONFIG_NOT_COHERENT_CACHE */
194 #endif /* CONFIG_SPECIAL_CONSISTENT_MEMORY */
197 #define CPU_PIPE_FLUSH \
199 __asm__ __volatile__ ("eieio"); \
205 /* Default port configuration value */
206 #define PORT_CONFIG_VALUE \
207 ETH_UNICAST_NORMAL_MODE | \
208 ETH_DEFAULT_RX_QUEUE_0 | \
209 ETH_DEFAULT_RX_ARP_QUEUE_0 | \
210 ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
211 ETH_RECEIVE_BC_IF_IP | \
212 ETH_RECEIVE_BC_IF_ARP | \
213 ETH_CAPTURE_TCP_FRAMES_DIS | \
214 ETH_CAPTURE_UDP_FRAMES_DIS | \
215 ETH_DEFAULT_RX_TCP_QUEUE_0 | \
216 ETH_DEFAULT_RX_UDP_QUEUE_0 | \
217 ETH_DEFAULT_RX_BPDU_QUEUE_0
219 /* Default port extend configuration value */
220 #define PORT_CONFIG_EXTEND_VALUE \
221 ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
222 ETH_PARTITION_DISABLE
225 /* Default sdma control value */
226 #ifdef CONFIG_NOT_COHERENT_CACHE
227 #define PORT_SDMA_CONFIG_VALUE \
228 ETH_RX_BURST_SIZE_16_64BIT | \
229 GT_ETH_IPG_INT_RX(0) | \
230 ETH_TX_BURST_SIZE_16_64BIT;
232 #define PORT_SDMA_CONFIG_VALUE \
233 ETH_RX_BURST_SIZE_4_64BIT | \
234 GT_ETH_IPG_INT_RX(0) | \
235 ETH_TX_BURST_SIZE_4_64BIT;
238 #define GT_ETH_IPG_INT_RX(value) \
239 ((value & 0x3fff) << 8)
241 /* Default port serial control value */
242 #define PORT_SERIAL_CONTROL_VALUE \
243 ETH_FORCE_LINK_PASS | \
244 ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
245 ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
246 ETH_ADV_SYMMETRIC_FLOW_CTRL | \
247 ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
248 ETH_FORCE_BP_MODE_NO_JAM | \
250 ETH_DO_NOT_FORCE_LINK_FAIL | \
251 ETH_RETRANSMIT_16_ETTEMPTS | \
252 ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
254 ETH_DISABLE_AUTO_NEG_BYPASS | \
255 ETH_AUTO_NEG_NO_CHANGE | \
256 ETH_MAX_RX_PACKET_1552BYTE | \
257 ETH_CLR_EXT_LOOPBACK | \
258 ETH_SET_FULL_DUPLEX_MODE | \
259 ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX;
261 #define RX_BUFFER_MAX_SIZE 0xFFFF
262 #define TX_BUFFER_MAX_SIZE 0xFFFF /* Buffer are limited to 64k */
264 #define RX_BUFFER_MIN_SIZE 0x8
265 #define TX_BUFFER_MIN_SIZE 0x8
267 /* Tx WRR confoguration macros */
268 #define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
269 #define PORT_MAX_TOKEN_BUCKET_SIZE 0x_fFFF /* PMTBS register (default) */
270 #define PORT_TOKEN_RATE 1023 /* PTTBRC register (default) */
272 /* MAC accepet/reject macros */
273 #define ACCEPT_MAC_ADDR 0
274 #define REJECT_MAC_ADDR 1
276 /* Size of a Tx/Rx descriptor used in chain list data structure */
277 #define RX_DESC_ALIGNED_SIZE 0x20
278 #define TX_DESC_ALIGNED_SIZE 0x20
280 /* An offest in Tx descriptors to store data for buffers less than 8 Bytes */
281 #define TX_BUF_OFFSET_IN_DESC 0x18
282 /* Buffer offset from buffer pointer */
283 #define RX_BUF_OFFSET 0x2
286 #define ETH_BAR_GAP 0x8
287 #define ETH_SIZE_REG_GAP 0x8
288 #define ETH_HIGH_ADDR_REMAP_REG_GAP 0x4
289 #define ETH_PORT_ACCESS_CTRL_GAP 0x4
291 /* Gigabit Ethernet Unit Global Registers */
293 /* MIB Counters register definitions */
294 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
295 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
296 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
297 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
298 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
299 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
300 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
301 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
302 #define ETH_MIB_FRAMES_64_OCTETS 0x20
303 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
304 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
305 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
306 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
307 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
308 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
309 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
310 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
311 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
312 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
313 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
314 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
315 #define ETH_MIB_FC_SENT 0x54
316 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
317 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
318 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
319 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
320 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
321 #define ETH_MIB_JABBER_RECEIVED 0x6c
322 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
323 #define ETH_MIB_BAD_CRC_EVENT 0x74
324 #define ETH_MIB_COLLISION 0x78
325 #define ETH_MIB_LATE_COLLISION 0x7c
327 /* Port serial status reg (PSR) */
328 #define ETH_INTERFACE_GMII_MII 0
329 #define ETH_INTERFACE_PCM BIT0
330 #define ETH_LINK_IS_DOWN 0
331 #define ETH_LINK_IS_UP BIT1
332 #define ETH_PORT_AT_HALF_DUPLEX 0
333 #define ETH_PORT_AT_FULL_DUPLEX BIT2
334 #define ETH_RX_FLOW_CTRL_DISABLED 0
335 #define ETH_RX_FLOW_CTRL_ENBALED BIT3
336 #define ETH_GMII_SPEED_100_10 0
337 #define ETH_GMII_SPEED_1000 BIT4
338 #define ETH_MII_SPEED_10 0
339 #define ETH_MII_SPEED_100 BIT5
341 #define ETH_TX_IN_PROGRESS BIT7
342 #define ETH_BYPASS_NO_ACTIVE 0
343 #define ETH_BYPASS_ACTIVE BIT8
344 #define ETH_PORT_NOT_AT_PARTITION_STATE 0
345 #define ETH_PORT_AT_PARTITION_STATE BIT9
346 #define ETH_PORT_TX_FIFO_NOT_EMPTY 0
347 #define ETH_PORT_TX_FIFO_EMPTY BIT10
350 /* These macros describes the Port configuration reg (Px_cR) bits */
351 #define ETH_UNICAST_NORMAL_MODE 0
352 #define ETH_UNICAST_PROMISCUOUS_MODE BIT0
353 #define ETH_DEFAULT_RX_QUEUE_0 0
354 #define ETH_DEFAULT_RX_QUEUE_1 BIT1
355 #define ETH_DEFAULT_RX_QUEUE_2 BIT2
356 #define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
357 #define ETH_DEFAULT_RX_QUEUE_4 BIT3
358 #define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
359 #define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
360 #define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
361 #define ETH_DEFAULT_RX_ARP_QUEUE_0 0
362 #define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
363 #define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
364 #define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
365 #define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
366 #define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
367 #define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
368 #define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
369 #define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
370 #define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
371 #define ETH_RECEIVE_BC_IF_IP 0
372 #define ETH_REJECT_BC_IF_IP BIT8
373 #define ETH_RECEIVE_BC_IF_ARP 0
374 #define ETH_REJECT_BC_IF_ARP BIT9
375 #define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
376 #define ETH_CAPTURE_TCP_FRAMES_DIS 0
377 #define ETH_CAPTURE_TCP_FRAMES_EN BIT14
378 #define ETH_CAPTURE_UDP_FRAMES_DIS 0
379 #define ETH_CAPTURE_UDP_FRAMES_EN BIT15
380 #define ETH_DEFAULT_RX_TCP_QUEUE_0 0
381 #define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
382 #define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
383 #define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
384 #define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
385 #define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
386 #define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
387 #define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
388 #define ETH_DEFAULT_RX_UDP_QUEUE_0 0
389 #define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
390 #define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
391 #define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
392 #define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
393 #define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
394 #define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
395 #define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
396 #define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
397 #define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
398 #define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
399 #define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
400 #define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
401 #define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
402 #define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
403 #define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
406 /* These macros describes the Port configuration extend reg (Px_cXR) bits*/
407 #define ETH_CLASSIFY_EN BIT0
408 #define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
409 #define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
410 #define ETH_PARTITION_DISABLE 0
411 #define ETH_PARTITION_ENABLE BIT2
414 /* Tx/Rx queue command reg (RQCR/TQCR)*/
415 #define ETH_QUEUE_0_ENABLE BIT0
416 #define ETH_QUEUE_1_ENABLE BIT1
417 #define ETH_QUEUE_2_ENABLE BIT2
418 #define ETH_QUEUE_3_ENABLE BIT3
419 #define ETH_QUEUE_4_ENABLE BIT4
420 #define ETH_QUEUE_5_ENABLE BIT5
421 #define ETH_QUEUE_6_ENABLE BIT6
422 #define ETH_QUEUE_7_ENABLE BIT7
423 #define ETH_QUEUE_0_DISABLE BIT8
424 #define ETH_QUEUE_1_DISABLE BIT9
425 #define ETH_QUEUE_2_DISABLE BIT10
426 #define ETH_QUEUE_3_DISABLE BIT11
427 #define ETH_QUEUE_4_DISABLE BIT12
428 #define ETH_QUEUE_5_DISABLE BIT13
429 #define ETH_QUEUE_6_DISABLE BIT14
430 #define ETH_QUEUE_7_DISABLE BIT15
432 /* These macros describes the Port Sdma configuration reg (SDCR) bits */
433 #define ETH_RIFB BIT0
434 #define ETH_RX_BURST_SIZE_1_64BIT 0
435 #define ETH_RX_BURST_SIZE_2_64BIT BIT1
436 #define ETH_RX_BURST_SIZE_4_64BIT BIT2
437 #define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
438 #define ETH_RX_BURST_SIZE_16_64BIT BIT3
439 #define ETH_BLM_RX_NO_SWAP BIT4
440 #define ETH_BLM_RX_BYTE_SWAP 0
441 #define ETH_BLM_TX_NO_SWAP BIT5
442 #define ETH_BLM_TX_BYTE_SWAP 0
443 #define ETH_DESCRIPTORS_BYTE_SWAP BIT6
444 #define ETH_DESCRIPTORS_NO_SWAP 0
445 #define ETH_TX_BURST_SIZE_1_64BIT 0
446 #define ETH_TX_BURST_SIZE_2_64BIT BIT22
447 #define ETH_TX_BURST_SIZE_4_64BIT BIT23
448 #define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
449 #define ETH_TX_BURST_SIZE_16_64BIT BIT24
451 /* These macros describes the Port serial control reg (PSCR) bits */
452 #define ETH_SERIAL_PORT_DISABLE 0
453 #define ETH_SERIAL_PORT_ENABLE BIT0
454 #define ETH_FORCE_LINK_PASS BIT1
455 #define ETH_DO_NOT_FORCE_LINK_PASS 0
456 #define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
457 #define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
458 #define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
459 #define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
460 #define ETH_ADV_NO_FLOW_CTRL 0
461 #define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
462 #define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
463 #define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
464 #define ETH_FORCE_BP_MODE_NO_JAM 0
465 #define ETH_FORCE_BP_MODE_JAM_TX BIT7
466 #define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
467 #define ETH_FORCE_LINK_FAIL 0
468 #define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
469 #define ETH_RETRANSMIT_16_ETTEMPTS 0
470 #define ETH_RETRANSMIT_FOREVER BIT11
471 #define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
472 #define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
473 #define ETH_DTE_ADV_0 0
474 #define ETH_DTE_ADV_1 BIT14
475 #define ETH_DISABLE_AUTO_NEG_BYPASS 0
476 #define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
477 #define ETH_AUTO_NEG_NO_CHANGE 0
478 #define ETH_RESTART_AUTO_NEG BIT16
479 #define ETH_MAX_RX_PACKET_1518BYTE 0
480 #define ETH_MAX_RX_PACKET_1522BYTE BIT17
481 #define ETH_MAX_RX_PACKET_1552BYTE BIT18
482 #define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
483 #define ETH_MAX_RX_PACKET_9192BYTE BIT19
484 #define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
485 #define ETH_SET_EXT_LOOPBACK BIT20
486 #define ETH_CLR_EXT_LOOPBACK 0
487 #define ETH_SET_FULL_DUPLEX_MODE BIT21
488 #define ETH_SET_HALF_DUPLEX_MODE 0
489 #define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
490 #define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
491 #define ETH_SET_GMII_SPEED_TO_10_100 0
492 #define ETH_SET_GMII_SPEED_TO_1000 BIT23
493 #define ETH_SET_MII_SPEED_TO_10 0
494 #define ETH_SET_MII_SPEED_TO_100 BIT24
498 #define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
499 #define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
500 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
501 #define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
503 /* SDMA command status fields macros */
505 /* Tx & Rx descriptors status */
506 #define ETH_ERROR_SUMMARY (BIT0)
508 /* Tx & Rx descriptors command */
509 #define ETH_BUFFER_OWNED_BY_DMA (BIT31)
511 /* Tx descriptors status */
512 #define ETH_LC_ERROR (0 )
513 #define ETH_UR_ERROR (BIT1 )
514 #define ETH_RL_ERROR (BIT2 )
515 #define ETH_LLC_SNAP_FORMAT (BIT9 )
517 /* Rx descriptors status */
518 #define ETH_CRC_ERROR (0 )
519 #define ETH_OVERRUN_ERROR (BIT1 )
520 #define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
521 #define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
522 #define ETH_VLAN_TAGGED (BIT19)
523 #define ETH_BPDU_FRAME (BIT20)
524 #define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
525 #define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
526 #define ETH_OTHER_FRAME_TYPE (BIT22)
527 #define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
528 #define ETH_FRAME_TYPE_IP_V_4 (BIT24)
529 #define ETH_FRAME_HEADER_OK (BIT25)
530 #define ETH_RX_LAST_DESC (BIT26)
531 #define ETH_RX_FIRST_DESC (BIT27)
532 #define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
533 #define ETH_RX_ENABLE_INTERRUPT (BIT29)
534 #define ETH_LAYER_4_CHECKSUM_OK (BIT30)
536 /* Rx descriptors byte count */
537 #define ETH_FRAME_FRAGMENTED (BIT2)
539 /* Tx descriptors command */
540 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
541 #define ETH_FRAME_SET_TO_VLAN (BIT15)
542 #define ETH_TCP_FRAME (0 )
543 #define ETH_UDP_FRAME (BIT16)
544 #define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
545 #define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
546 #define ETH_ZERO_PADDING (BIT19)
547 #define ETH_TX_LAST_DESC (BIT20)
548 #define ETH_TX_FIRST_DESC (BIT21)
549 #define ETH_GEN_CRC (BIT22)
550 #define ETH_TX_ENABLE_INTERRUPT (BIT23)
551 #define ETH_AUTO_MODE (BIT30)
553 /* Address decode parameters */
554 /* Ethernet Base Address Register bits */
555 #define EBAR_TARGET_DRAM 0x00000000
556 #define EBAR_TARGET_DEVICE 0x00000001
557 #define EBAR_TARGET_CBS 0x00000002
558 #define EBAR_TARGET_PCI0 0x00000003
559 #define EBAR_TARGET_PCI1 0x00000004
560 #define EBAR_TARGET_CUNIT 0x00000005
561 #define EBAR_TARGET_AUNIT 0x00000006
562 #define EBAR_TARGET_GUNIT 0x00000007
564 /* Window attributes */
565 #define EBAR_ATTR_DRAM_CS0 0x00000E00
566 #define EBAR_ATTR_DRAM_CS1 0x00000D00
567 #define EBAR_ATTR_DRAM_CS2 0x00000B00
568 #define EBAR_ATTR_DRAM_CS3 0x00000700
570 /* DRAM Target interface */
571 #define EBAR_ATTR_DRAM_NO_CACHE_COHERENCY 0x00000000
572 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WT 0x00001000
573 #define EBAR_ATTR_DRAM_CACHE_COHERENCY_WB 0x00002000
575 /* Device Bus Target interface */
576 #define EBAR_ATTR_DEVICE_DEVCS0 0x00001E00
577 #define EBAR_ATTR_DEVICE_DEVCS1 0x00001D00
578 #define EBAR_ATTR_DEVICE_DEVCS2 0x00001B00
579 #define EBAR_ATTR_DEVICE_DEVCS3 0x00001700
580 #define EBAR_ATTR_DEVICE_BOOTCS3 0x00000F00
582 /* PCI Target interface */
583 #define EBAR_ATTR_PCI_BYTE_SWAP 0x00000000
584 #define EBAR_ATTR_PCI_NO_SWAP 0x00000100
585 #define EBAR_ATTR_PCI_BYTE_WORD_SWAP 0x00000200
586 #define EBAR_ATTR_PCI_WORD_SWAP 0x00000300
587 #define EBAR_ATTR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
588 #define EBAR_ATTR_PCI_NO_SNOOP_ASSERT 0x00000400
589 #define EBAR_ATTR_PCI_IO_SPACE 0x00000000
590 #define EBAR_ATTR_PCI_MEMORY_SPACE 0x00000800
591 #define EBAR_ATTR_PCI_REQ64_FORCE 0x00000000
592 #define EBAR_ATTR_PCI_REQ64_SIZE 0x00001000
594 /* CPU 60x bus or internal SRAM interface */
595 #define EBAR_ATTR_CBS_SRAM_BLOCK0 0x00000000
596 #define EBAR_ATTR_CBS_SRAM_BLOCK1 0x00000100
597 #define EBAR_ATTR_CBS_SRAM 0x00000000
598 #define EBAR_ATTR_CBS_CPU_BUS 0x00000800
600 /* Window access control */
601 #define EWIN_ACCESS_NOT_ALLOWED 0
602 #define EWIN_ACCESS_READ_ONLY BIT0
603 #define EWIN_ACCESS_FULL (BIT1 | BIT0)
604 #define EWIN0_ACCESS_MASK 0x0003
605 #define EWIN1_ACCESS_MASK 0x000C
606 #define EWIN2_ACCESS_MASK 0x0030
607 #define EWIN3_ACCESS_MASK 0x00C0
611 typedef enum _eth_port
618 typedef enum _eth_func_ret_status
620 ETH_OK, /* Returned as expected. */
621 ETH_ERROR, /* Fundamental error. */
622 ETH_RETRY, /* Could not process request. Try later. */
623 ETH_END_OF_JOB, /* Ring has nothing to process. */
624 ETH_QUEUE_FULL, /* Ring resource error. */
625 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
626 }ETH_FUNC_RET_STATUS;
628 typedef enum _eth_queue
640 typedef enum _addr_win
650 typedef enum _eth_target
659 typedef struct _eth_rx_desc
661 unsigned short byte_cnt ; /* Descriptor buffer byte count */
662 unsigned short buf_size ; /* Buffer size */
663 unsigned int cmd_sts ; /* Descriptor command status */
664 unsigned int next_desc_ptr; /* Next descriptor pointer */
665 unsigned int buf_ptr ; /* Descriptor buffer pointer */
666 unsigned int return_info ; /* User resource return information */
670 typedef struct _eth_tx_desc
672 unsigned short byte_cnt ; /* Descriptor buffer byte count */
673 unsigned short l4i_chk ; /* CPU provided TCP Checksum */
674 unsigned int cmd_sts ; /* Descriptor command status */
675 unsigned int next_desc_ptr; /* Next descriptor pointer */
676 unsigned int buf_ptr ; /* Descriptor buffer pointer */
677 unsigned int return_info ; /* User resource return information */
680 /* Unified struct for Rx and Tx operations. The user is not required to */
681 /* be familier with neither Tx nor Rx descriptors. */
682 typedef struct _pkt_info
684 unsigned short byte_cnt ; /* Descriptor buffer byte count */
685 unsigned short l4i_chk ; /* Tx CPU provided TCP Checksum */
686 unsigned int cmd_sts ; /* Descriptor command status */
687 unsigned int buf_ptr ; /* Descriptor buffer pointer */
688 unsigned int return_info ; /* User resource return information */
692 typedef struct _eth_win_param
694 ETH_ADDR_WIN win; /* Window number. See ETH_ADDR_WIN enum */
695 ETH_TARGET target; /* System targets. See ETH_TARGET enum */
696 unsigned short attributes; /* BAR attributes. See above macros. */
697 unsigned int base_addr; /* Window base address in unsigned int form */
698 unsigned int high_addr; /* Window high address in unsigned int form */
699 unsigned int size; /* Size in MBytes. Must be % 64Kbyte. */
700 bool enable; /* Enable/disable access to the window. */
701 unsigned short access_ctrl; /* Access ctrl register. see above macros */
705 /* Ethernet port specific infomation */
707 typedef struct _eth_port_ctrl
709 ETH_PORT port_num; /* User Ethernet port number */
710 int port_phy_addr; /* User phy address of Ethrnet port */
711 unsigned char port_mac_addr[6]; /* User defined port MAC address. */
712 unsigned int port_config; /* User port configuration value */
713 unsigned int port_config_extend; /* User port config extend value */
714 unsigned int port_sdma_config; /* User port SDMA config value */
715 unsigned int port_serial_control; /* User port serial control value */
716 unsigned int port_tx_queue_command; /* Port active Tx queues summary */
717 unsigned int port_rx_queue_command; /* Port active Rx queues summary */
719 /* User function to cast virtual address to CPU bus address */
720 unsigned int (*port_virt_to_phys)(unsigned int addr);
721 /* User scratch pad for user specific data structures */
724 bool rx_resource_err[MAX_RX_QUEUE_NUM]; /* Rx ring resource error flag */
725 bool tx_resource_err[MAX_TX_QUEUE_NUM]; /* Tx ring resource error flag */
727 /* Tx/Rx rings managment indexes fields. For driver use */
729 /* Next available Rx resource */
730 volatile ETH_RX_DESC *p_rx_curr_desc_q[MAX_RX_QUEUE_NUM];
731 /* Returning Rx resource */
732 volatile ETH_RX_DESC *p_rx_used_desc_q[MAX_RX_QUEUE_NUM];
734 /* Next available Tx resource */
735 volatile ETH_TX_DESC *p_tx_curr_desc_q[MAX_TX_QUEUE_NUM];
736 /* Returning Tx resource */
737 volatile ETH_TX_DESC *p_tx_used_desc_q[MAX_TX_QUEUE_NUM];
738 /* An extra Tx index to support transmit of multiple buffers per packet */
739 volatile ETH_TX_DESC *p_tx_first_desc_q[MAX_TX_QUEUE_NUM];
741 /* Tx/Rx rings size and base variables fields. For driver use */
743 volatile ETH_RX_DESC *p_rx_desc_area_base[MAX_RX_QUEUE_NUM];
744 unsigned int rx_desc_area_size[MAX_RX_QUEUE_NUM];
745 char *p_rx_buffer_base[MAX_RX_QUEUE_NUM];
747 volatile ETH_TX_DESC *p_tx_desc_area_base[MAX_TX_QUEUE_NUM];
748 unsigned int tx_desc_area_size[MAX_TX_QUEUE_NUM];
749 char *p_tx_buffer_base[MAX_TX_QUEUE_NUM];
754 /* ethernet.h API list */
756 /* Port operation control routines */
757 static void eth_port_init (ETH_PORT_INFO *p_eth_port_ctrl);
758 static void eth_port_reset(ETH_PORT eth_port_num);
759 static bool eth_port_start(ETH_PORT_INFO *p_eth_port_ctrl);
762 /* Port MAC address routines */
763 static void eth_port_uc_addr_set (ETH_PORT eth_port_num,
764 unsigned char *p_addr,
767 static void eth_port_mc_addr (ETH_PORT eth_port_num,
768 unsigned char *p_addr,
773 /* PHY and MIB routines */
774 static bool ethernet_phy_reset(ETH_PORT eth_port_num);
776 static bool eth_port_write_smi_reg(ETH_PORT eth_port_num,
777 unsigned int phy_reg,
780 static bool eth_port_read_smi_reg(ETH_PORT eth_port_num,
781 unsigned int phy_reg,
782 unsigned int* value);
784 static void eth_clear_mib_counters(ETH_PORT eth_port_num);
786 /* Port data flow control routines */
787 static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO *p_eth_port_ctrl,
789 PKT_INFO *p_pkt_info);
790 static ETH_FUNC_RET_STATUS eth_tx_return_desc(ETH_PORT_INFO *p_eth_port_ctrl,
792 PKT_INFO *p_pkt_info);
793 static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO *p_eth_port_ctrl,
795 PKT_INFO *p_pkt_info);
796 static ETH_FUNC_RET_STATUS eth_rx_return_buff(ETH_PORT_INFO *p_eth_port_ctrl,
798 PKT_INFO *p_pkt_info);
801 static bool ether_init_tx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
805 unsigned int tx_desc_base_addr,
806 unsigned int tx_buff_base_addr);
808 static bool ether_init_rx_desc_ring(ETH_PORT_INFO *p_eth_port_ctrl,
812 unsigned int rx_desc_base_addr,
813 unsigned int rx_buff_base_addr);
815 #endif /* MV64460_ETH_ */