3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* PCI.c - PCI functions */
32 int pciauto_region_allocate(struct pci_region* res, unsigned int size, unsigned int *bar);
35 #include "../../Marvell/include/pci.h"
38 #undef IDE_SET_NATIVE_MODE
39 static unsigned int local_buses[] = { 0, 0 };
41 static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
42 {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
43 {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
46 #ifdef CONFIG_USE_CPCIDVI
52 static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
56 static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
57 static void gt_pci_bus_mode_display (PCI_HOST host)
62 mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
65 printf ("PCI %d bus mode: Conventional PCI\n", host);
68 printf ("PCI %d bus mode: 66 MHz PCIX\n", host);
71 printf ("PCI %d bus mode: 100 MHz PCIX\n", host);
74 printf ("PCI %d bus mode: 133 MHz PCIX\n", host);
77 printf ("Unknown BUS %d\n", mode);
82 static const unsigned int pci_p2p_configuration_reg[] = {
83 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
86 static const unsigned int pci_configuration_address[] = {
87 PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
90 static const unsigned int pci_configuration_data[] = {
91 PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
92 PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
95 static const unsigned int pci_error_cause_reg[] = {
96 PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
99 static const unsigned int pci_arbiter_control[] = {
100 PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
103 static const unsigned int pci_address_space_en[] = {
104 PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
107 static const unsigned int pci_snoop_control_base_0_low[] = {
108 PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
110 static const unsigned int pci_snoop_control_top_0[] = {
111 PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
114 static const unsigned int pci_access_control_base_0_low[] = {
115 PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
117 static const unsigned int pci_access_control_top_0[] = {
118 PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
121 static const unsigned int pci_scs_bank_size[2][4] = {
122 {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
123 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
124 {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
125 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
128 static const unsigned int pci_p2p_configuration[] = {
129 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
133 /********************************************************************
134 * pciWriteConfigReg - Write to a PCI configuration register
135 * - Make sure the GT is configured as a master before writing
136 * to another device on the PCI.
137 * - The function takes care of Big/Little endian conversion.
140 * Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
141 * (or any other PCI device spec)
142 * pciDevNum: The device number needs to be addressed.
144 * Configuration Address 0xCF8:
146 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
147 * |congif|Reserved| Bus |Device|Function|Register|00|
148 * |Enable| |Number|Number| Number | Number | | <=field Name
150 *********************************************************************/
151 void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
152 unsigned int pciDevNum, unsigned int data)
154 volatile unsigned int DataForAddrReg;
155 unsigned int functionNum;
156 unsigned int busNum = 0;
159 if (pciDevNum > 32) /* illegal device Number */
161 if (pciDevNum == SELF) { /* configure our configuration space. */
163 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
165 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
168 functionNum = regOffset & 0x00000700;
169 pciDevNum = pciDevNum << 11;
170 regOffset = regOffset & 0xfc;
172 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
173 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
174 GT_REG_READ (pci_configuration_address[host], &addr);
175 if (addr != DataForAddrReg)
177 GT_REG_WRITE (pci_configuration_data[host], data);
180 /********************************************************************
181 * pciReadConfigReg - Read from a PCI0 configuration register
182 * - Make sure the GT is configured as a master before reading
183 * from another device on the PCI.
184 * - The function takes care of Big/Little endian conversion.
185 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
187 * pciDevNum: The device number needs to be addressed.
188 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
189 * cause register to make sure the data is valid
191 * Configuration Address 0xCF8:
193 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
194 * |congif|Reserved| Bus |Device|Function|Register|00|
195 * |Enable| |Number|Number| Number | Number | | <=field Name
197 *********************************************************************/
198 unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
199 unsigned int pciDevNum)
201 volatile unsigned int DataForAddrReg;
203 unsigned int functionNum;
204 unsigned int busNum = 0;
206 if (pciDevNum > 32) /* illegal device Number */
208 if (pciDevNum == SELF) { /* configure our configuration space. */
210 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
212 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
215 functionNum = regOffset & 0x00000700;
216 pciDevNum = pciDevNum << 11;
217 regOffset = regOffset & 0xfc;
219 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
220 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
221 GT_REG_READ (pci_configuration_address[host], &data);
222 if (data != DataForAddrReg)
224 GT_REG_READ (pci_configuration_data[host], &data);
228 /********************************************************************
229 * pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
230 * the agent is placed on another Bus. For more
231 * information read P2P in the PCI spec.
233 * Inputs: unsigned int regOffset - The register offset as it apears in the
234 * GT spec (or any other PCI device spec).
235 * unsigned int pciDevNum - The device number needs to be addressed.
236 * unsigned int busNum - On which bus does the Target agent connect
238 * unsigned int data - data to be written.
240 * Configuration Address 0xCF8:
242 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
243 * |congif|Reserved| Bus |Device|Function|Register|01|
244 * |Enable| |Number|Number| Number | Number | | <=field Name
246 * The configuration Address is configure as type-I (bits[1:0] = '01') due to
247 * PCI spec referring to P2P.
249 *********************************************************************/
250 void pciOverBridgeWriteConfigReg (PCI_HOST host,
251 unsigned int regOffset,
252 unsigned int pciDevNum,
253 unsigned int busNum, unsigned int data)
255 unsigned int DataForReg;
256 unsigned int functionNum;
258 functionNum = regOffset & 0x00000700;
259 pciDevNum = pciDevNum << 11;
260 regOffset = regOffset & 0xff;
261 busNum = busNum << 16;
262 if (pciDevNum == SELF) { /* This board */
263 DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
265 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
268 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
269 GT_REG_WRITE (pci_configuration_data[host], data);
273 /********************************************************************
274 * pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
275 * the agent target locate on another PCI bus.
276 * - Make sure the GT is configured as a master
277 * before reading from another device on the PCI.
278 * - The function takes care of Big/Little endian
280 * INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
281 * spec). (configuration register offset.)
282 * pciDevNum: The device number needs to be addressed.
283 * busNum: the Bus number where the agent is place.
284 * RETURNS: data , if the data == 0xffffffff check the master abort bit in the
285 * cause register to make sure the data is valid
287 * Configuration Address 0xCF8:
289 * 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
290 * |congif|Reserved| Bus |Device|Function|Register|01|
291 * |Enable| |Number|Number| Number | Number | | <=field Name
293 *********************************************************************/
294 unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
295 unsigned int regOffset,
296 unsigned int pciDevNum,
299 unsigned int DataForReg;
301 unsigned int functionNum;
303 functionNum = regOffset & 0x00000700;
304 pciDevNum = pciDevNum << 11;
305 regOffset = regOffset & 0xff;
306 busNum = busNum << 16;
307 if (pciDevNum == SELF) { /* This board */
308 DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
309 } else { /* agent on another bus */
311 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
314 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
315 GT_REG_READ (pci_configuration_data[host], &data);
320 /********************************************************************
321 * pciGetRegOffset - Gets the register offset for this region config.
323 * INPUT: Bus, Region - The bus and region we ask for its base address.
325 * RETURNS: PCI register base address
326 *********************************************************************/
327 static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
333 return PCI_0I_O_LOW_DECODE_ADDRESS;
335 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
337 return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
339 return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
341 return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
346 return PCI_1I_O_LOW_DECODE_ADDRESS;
348 return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
350 return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
352 return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
354 return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
357 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
360 static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
366 return PCI_0I_O_ADDRESS_REMAP;
368 return PCI_0MEMORY0_ADDRESS_REMAP;
370 return PCI_0MEMORY1_ADDRESS_REMAP;
372 return PCI_0MEMORY2_ADDRESS_REMAP;
374 return PCI_0MEMORY3_ADDRESS_REMAP;
379 return PCI_1I_O_ADDRESS_REMAP;
381 return PCI_1MEMORY0_ADDRESS_REMAP;
383 return PCI_1MEMORY1_ADDRESS_REMAP;
385 return PCI_1MEMORY2_ADDRESS_REMAP;
387 return PCI_1MEMORY3_ADDRESS_REMAP;
390 return PCI_0MEMORY0_ADDRESS_REMAP;
393 /********************************************************************
394 * pciGetBaseAddress - Gets the base address of a PCI.
395 * - If the PCI size is 0 then this base address has no meaning!!!
398 * INPUT: Bus, Region - The bus and region we ask for its base address.
400 * RETURNS: PCI base address.
401 *********************************************************************/
402 unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
404 unsigned int regBase;
406 unsigned int regOffset = pciGetRegOffset (host, region);
408 GT_REG_READ (regOffset, ®Base);
409 GT_REG_READ (regOffset + 8, ®End);
411 if (regEnd <= regBase)
412 return 0xffffffff; /* ERROR !!! */
414 regBase = regBase << 16;
418 bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
419 unsigned int bankBase, unsigned int bankLength)
421 unsigned int low = 0xfff;
422 unsigned int high = 0x0;
423 unsigned int regOffset = pciGetRegOffset (host, region);
424 unsigned int remapOffset = pciGetRemapOffset (host, region);
426 if (bankLength != 0) {
427 low = (bankBase >> 16) & 0xffff;
428 high = ((bankBase + bankLength) >> 16) - 1;
431 GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
432 GT_REG_WRITE (regOffset + 8, high);
434 if (bankLength != 0) { /* must do AFTER writing maps */
435 GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
436 dont support upper 32
442 unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
445 unsigned int regOffset = pciGetRegOffset (host, region);
447 GT_REG_READ (regOffset, &low);
448 return (low & 0xffff) << 16;
451 unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
453 unsigned int low, high;
454 unsigned int regOffset = pciGetRegOffset (host, region);
456 GT_REG_READ (regOffset, &low);
457 GT_REG_READ (regOffset + 8, &high);
458 return ((high & 0xffff) + 1) << 16;
462 /* ronen - 7/Dec/03*/
463 /********************************************************************
464 * gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
465 * Inputs: one of the PCI BAR
466 *********************************************************************/
467 void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
469 RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
472 void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
474 SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
477 /********************************************************************
478 * pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
480 * Inputs: base and size of PCI SCS
481 *********************************************************************/
482 void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
483 unsigned int pciDramBase, unsigned int pciDramSize)
485 /*ronen different function for 3rd bank. */
486 unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
488 pciDramBase = pciDramBase & 0xfffff000;
489 pciDramBase = pciDramBase | (pciReadConfigReg (host,
490 PCI_SCS_0_BASE_ADDRESS
493 pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
495 if (pciDramSize == 0)
497 GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
498 gtPciEnableInternalBAR (host, bank);
501 /********************************************************************
502 * pciSetRegionFeatures - This function modifys one of the 8 regions with
503 * feature bits given as an input.
504 * - Be advised to check the spec before modifying them.
505 * Inputs: PCI_PROTECT_REGION region - one of the eight regions.
506 * unsigned int features - See file: pci.h there are defintion for those
508 * unsigned int baseAddress - The region base Address.
509 * unsigned int topAddress - The region top Address.
510 * Returns: false if one of the parameters is erroneous true otherwise.
511 *********************************************************************/
512 bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
513 unsigned int features, unsigned int baseAddress,
514 unsigned int regionLength)
516 unsigned int accessLow;
517 unsigned int accessHigh;
518 unsigned int accessTop = baseAddress + regionLength;
520 if (regionLength == 0) { /* close the region. */
521 pciDisableAccessRegion (host, region);
524 /* base Address is store is bits [11:0] */
525 accessLow = (baseAddress & 0xfff00000) >> 20;
526 /* All the features are update according to the defines in pci.h (to be on
527 the safe side we disable bits: [11:0] */
528 accessLow = accessLow | (features & 0xfffff000);
529 /* write to the Low Access Region register */
530 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
533 accessHigh = (accessTop & 0xfff00000) >> 20;
535 /* write to the High Access Region register */
536 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
541 /********************************************************************
542 * pciDisableAccessRegion - Disable The given Region by writing MAX size
543 * to its low Address and MIN size to its high Address.
545 * Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
547 *********************************************************************/
548 void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
550 /* writing back the registers default values. */
551 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
553 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
556 /********************************************************************
557 * pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
561 *********************************************************************/
562 bool pciArbiterEnable (PCI_HOST host)
564 unsigned int regData;
566 GT_REG_READ (pci_arbiter_control[host], ®Data);
567 GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
571 /********************************************************************
572 * pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
576 *********************************************************************/
577 bool pciArbiterDisable (PCI_HOST host)
579 unsigned int regData;
581 GT_REG_READ (pci_arbiter_control[host], ®Data);
582 GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
586 /********************************************************************
587 * pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
589 * Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
590 * PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
591 * PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
592 * PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
593 * PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
594 * PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
595 * PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
597 *********************************************************************/
598 bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
599 PCI_AGENT_PRIO externalAgent0,
600 PCI_AGENT_PRIO externalAgent1,
601 PCI_AGENT_PRIO externalAgent2,
602 PCI_AGENT_PRIO externalAgent3,
603 PCI_AGENT_PRIO externalAgent4,
604 PCI_AGENT_PRIO externalAgent5)
606 unsigned int regData;
607 unsigned int writeData;
609 GT_REG_READ (pci_arbiter_control[host], ®Data);
610 writeData = (internalAgent << 7) + (externalAgent0 << 8) +
611 (externalAgent1 << 9) + (externalAgent2 << 10) +
612 (externalAgent3 << 11) + (externalAgent4 << 12) +
613 (externalAgent5 << 13);
614 regData = (regData & 0xffffc07f) | writeData;
615 GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
619 /********************************************************************
620 * pciParkingDisable - Park on last option disable, with this function you can
621 * disable the park on last mechanism for each agent.
622 * disabling this option for all agents results parking
623 * on the internal master.
625 * Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
626 * PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
627 * PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
628 * PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
629 * PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
630 * PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
631 * PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
633 *********************************************************************/
634 bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
635 PCI_AGENT_PARK externalAgent0,
636 PCI_AGENT_PARK externalAgent1,
637 PCI_AGENT_PARK externalAgent2,
638 PCI_AGENT_PARK externalAgent3,
639 PCI_AGENT_PARK externalAgent4,
640 PCI_AGENT_PARK externalAgent5)
642 unsigned int regData;
643 unsigned int writeData;
645 GT_REG_READ (pci_arbiter_control[host], ®Data);
646 writeData = (internalAgent << 14) + (externalAgent0 << 15) +
647 (externalAgent1 << 16) + (externalAgent2 << 17) +
648 (externalAgent3 << 18) + (externalAgent4 << 19) +
649 (externalAgent5 << 20);
650 regData = (regData & ~(0x7f << 14)) | writeData;
651 GT_REG_WRITE (pci_arbiter_control[host], regData);
655 /********************************************************************
656 * pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
657 * respond to grant assertion within a window specified in
658 * the input value: 'brokenValue'.
660 * Inputs: unsigned char brokenValue - A value which limits the Master to hold the
661 * grant without asserting frame.
662 * Returns: Error for illegal broken value otherwise true.
663 *********************************************************************/
664 bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
667 unsigned int regData;
669 if (brokenValue > 0xf)
670 return false; /* brokenValue must be 4 bit */
671 data = brokenValue << 3;
672 GT_REG_READ (pci_arbiter_control[host], ®Data);
673 regData = (regData & 0xffffff87) | data;
674 GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
678 /********************************************************************
679 * pciDisableBrokenAgentDetection - This function disable the Broken agent
680 * Detection mechanism.
681 * NOTE: This operation may cause a dead lock on the
686 *********************************************************************/
687 bool pciDisableBrokenAgentDetection (PCI_HOST host)
689 unsigned int regData;
691 GT_REG_READ (pci_arbiter_control[host], ®Data);
692 regData = regData & 0xfffffffd;
693 GT_REG_WRITE (pci_arbiter_control[host], regData);
697 /********************************************************************
698 * pciP2PConfig - This function set the PCI_n P2P configurate.
699 * For more information on the P2P read PCI spec.
701 * Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
703 * unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
705 * unsigned int busNum - The CPI bus number to which the PCI interface
707 * unsigned int devNum - The PCI interface's device number.
710 *********************************************************************/
711 bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
712 unsigned int SecondBusHigh,
713 unsigned int busNum, unsigned int devNum)
715 unsigned int regData;
717 regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
718 ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
719 GT_REG_WRITE (pci_p2p_configuration[host], regData);
723 /********************************************************************
724 * pciSetRegionSnoopMode - This function modifys one of the 4 regions which
725 * supports Cache Coherency in the PCI_n interface.
726 * Inputs: region - One of the four regions.
727 * snoopType - There is four optional Types:
729 * 2. Snoop to WT region.
730 * 3. Snoop to WB region.
731 * 4. Snoop & Invalidate to WB region.
732 * baseAddress - Base Address of this region.
733 * regionLength - Region length.
734 * Returns: false if one of the parameters is wrong otherwise return true.
735 *********************************************************************/
736 bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
737 PCI_SNOOP_TYPE snoopType,
738 unsigned int baseAddress,
739 unsigned int regionLength)
741 unsigned int snoopXbaseAddress;
742 unsigned int snoopXtopAddress;
744 unsigned int snoopHigh = baseAddress + regionLength;
746 if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
749 pci_snoop_control_base_0_low[host] + 0x10 * region;
750 snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
751 if (regionLength == 0) { /* closing the region */
752 GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
753 GT_REG_WRITE (snoopXtopAddress, 0);
756 baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
757 data = (baseAddress >> 20) | snoopType << 12;
758 GT_REG_WRITE (snoopXbaseAddress, data);
759 snoopHigh = (snoopHigh & 0xfff00000) >> 20;
760 GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
764 static int gt_read_config_dword (struct pci_controller *hose,
765 pci_dev_t dev, int offset, u32 * value)
767 int bus = PCI_BUS (dev);
769 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
770 *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
773 *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
781 static int gt_write_config_dword (struct pci_controller *hose,
782 pci_dev_t dev, int offset, u32 value)
784 int bus = PCI_BUS (dev);
786 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
787 pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
788 PCI_DEV (dev), value);
790 pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
791 offset, PCI_DEV (dev), bus,
798 static void gt_setup_ide (struct pci_controller *hose,
799 pci_dev_t dev, struct pci_config_table *entry)
801 static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
802 u32 bar_response, bar_value;
805 for (bar = 0; bar < 6; bar++) {
806 /*ronen different function for 3rd bank. */
807 unsigned int offset =
808 (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
810 pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
812 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
815 pciauto_region_allocate (bar_response &
816 PCI_BASE_ADDRESS_SPACE_IO ? hose->
817 pci_io : hose->pci_mem, ide_bar[bar],
820 pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
825 #ifdef CONFIG_USE_CPCIDVI
826 static void gt_setup_cpcidvi (struct pci_controller *hose,
827 pci_dev_t dev, struct pci_config_table *entry)
829 u32 bar_value, pci_response;
831 pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
832 pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
833 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
834 pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
835 pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
836 pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
837 pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
838 pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
839 gt_cpcidvi_rom.base = bar_value & 0xffffff00;
840 gt_cpcidvi_rom.init = 1;
843 unsigned char gt_cpcidvi_in8(unsigned int offset)
847 if (gt_cpcidvi_rom.init == 0) {
850 data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
854 void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
858 if (gt_cpcidvi_rom.init == 0) {
862 off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
868 /* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
869 /* and is curently not called *. */
871 static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
873 unsigned char pin, irq;
875 pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
877 if (pin == 1) { /* only allow INT A */
878 irq = pci_irq_swizzle[(PCI_HOST) hose->
879 cfg_addr][PCI_DEV (dev)];
881 pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
886 struct pci_config_table gt_config_table[] = {
887 #ifdef CONFIG_USE_CPCIDVI
888 {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
889 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
891 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
892 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
896 struct pci_controller pci0_hose = {
897 /* fixup_irq: gt_fixup_irq, */
898 config_table:gt_config_table,
901 struct pci_controller pci1_hose = {
902 /* fixup_irq: gt_fixup_irq, */
903 config_table:gt_config_table,
906 void pci_init_board (void)
908 unsigned int command;
909 #ifdef CONFIG_PCI_PNP
913 gt_pci_bus_mode_display (PCI_HOST0);
915 #ifdef CONFIG_USE_CPCIDVI
916 gt_cpcidvi_rom.init = 0;
917 gt_cpcidvi_rom.base = 0;
920 pci0_hose.config_table = gt_config_table;
921 pci1_hose.config_table = gt_config_table;
923 #ifdef CONFIG_USE_CPCIDVI
924 gt_config_table[0].config_device = gt_setup_cpcidvi;
926 gt_config_table[1].config_device = gt_setup_ide;
928 pci0_hose.first_busno = 0;
929 pci0_hose.last_busno = 0xff;
930 local_buses[0] = pci0_hose.first_busno;
932 /* PCI memory space */
933 pci_set_region (pci0_hose.regions + 0,
934 CONFIG_SYS_PCI0_0_MEM_SPACE,
935 CONFIG_SYS_PCI0_0_MEM_SPACE,
936 CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
939 pci_set_region (pci0_hose.regions + 1,
940 CONFIG_SYS_PCI0_IO_SPACE_PCI,
941 CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
943 pci_set_ops (&pci0_hose,
944 pci_hose_read_config_byte_via_dword,
945 pci_hose_read_config_word_via_dword,
946 gt_read_config_dword,
947 pci_hose_write_config_byte_via_dword,
948 pci_hose_write_config_word_via_dword,
949 gt_write_config_dword);
950 pci0_hose.region_count = 2;
952 pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
954 pci_register_hose (&pci0_hose);
955 pciArbiterDisable(PCI_HOST0); /* on PMC modules no arbiter is used */
956 pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
957 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
958 command |= PCI_COMMAND_MASTER;
959 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
960 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
961 command |= PCI_COMMAND_MEMORY;
962 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
964 #ifdef CONFIG_PCI_PNP
965 pciauto_config_init(&pci0_hose);
966 pciauto_region_allocate(pci0_hose.pci_io, 0x400, &bar);
968 #ifdef CONFIG_PCI_SCAN_SHOW
969 printf("PCI: Bus Dev VenId DevId Class Int\n");
971 pci0_hose.last_busno = pci_hose_scan_bus (&pci0_hose, pci0_hose.first_busno);
974 gt_pci_bus_mode_display (PCI_HOST1);
976 pci1_hose.first_busno = pci0_hose.last_busno + 1;
977 pci1_hose.last_busno = 0xff;
978 pci1_hose.current_busno = pci1_hose.first_busno;
979 local_buses[1] = pci1_hose.first_busno;
981 /* PCI memory space */
982 pci_set_region (pci1_hose.regions + 0,
983 CONFIG_SYS_PCI1_0_MEM_SPACE,
984 CONFIG_SYS_PCI1_0_MEM_SPACE,
985 CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
988 pci_set_region (pci1_hose.regions + 1,
989 CONFIG_SYS_PCI1_IO_SPACE_PCI,
990 CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
992 pci_set_ops (&pci1_hose,
993 pci_hose_read_config_byte_via_dword,
994 pci_hose_read_config_word_via_dword,
995 gt_read_config_dword,
996 pci_hose_write_config_byte_via_dword,
997 pci_hose_write_config_word_via_dword,
998 gt_write_config_dword);
1000 pci1_hose.region_count = 2;
1002 pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
1004 pci_register_hose (&pci1_hose);
1006 pciArbiterEnable (PCI_HOST1);
1007 pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
1009 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
1010 command |= PCI_COMMAND_MASTER;
1011 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
1013 #ifdef CONFIG_PCI_PNP
1014 pciauto_config_init(&pci1_hose);
1015 pciauto_region_allocate(pci1_hose.pci_io, 0x400, &bar);
1017 pci1_hose.last_busno = pci_hose_scan_bus (&pci1_hose, pci1_hose.first_busno);
1019 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
1020 command |= PCI_COMMAND_MEMORY;
1021 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
1024 #endif /* of CONFIG_PCI */