3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/processor.h>
32 DECLARE_GLOBAL_DATA_PTR;
34 void set_led(int color)
38 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED);
42 out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED);
46 out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN);
50 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED);
55 static int is_monarch(void)
57 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY);
60 if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO)
66 static void wait_for_pci_ready(void)
69 * Configure EREADY_IO as input
71 out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO);
75 if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO)
81 int board_early_init_f(void)
85 /*--------------------------------------------------------------------
86 * Setup the external bus controller/chip selects
87 *-------------------------------------------------------------------*/
88 mtdcr(EBC0_CFGADDR, EBC0_CFG);
89 reg = mfdcr(EBC0_CFGDATA);
90 mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
92 /*--------------------------------------------------------------------
93 * Setup pin multiplexing (GPIO/IRQ...)
94 *-------------------------------------------------------------------*/
95 mtdcr(CPC0_GPIO, 0x03F01F80);
97 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
98 out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN);
99 out32(GPIO0_OR, CONFIG_SYS_GPIO_RDY);
101 /*--------------------------------------------------------------------
102 * Setup the interrupt controller polarities, triggers, etc.
103 *-------------------------------------------------------------------*/
104 mtdcr(UIC0SR, 0xffffffff); /* clear all */
105 mtdcr(UIC0ER, 0x00000000); /* disable all */
106 mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
107 mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
108 mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
109 mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
110 mtdcr(UIC0SR, 0xffffffff); /* clear all */
112 mtdcr(UIC1SR, 0xffffffff); /* clear all */
113 mtdcr(UIC1ER, 0x00000000); /* disable all */
114 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
115 mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
116 mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
117 mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
118 mtdcr(UIC1SR, 0xffffffff); /* clear all */
126 int i = getenv_f("serial#", buf, sizeof(buf));
128 printf("Board: P3P440");
137 puts(", None-Monarch");
145 int misc_init_r (void)
148 * Adjust flash start and offset to detected values
150 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
151 gd->bd->bi_flashoffset = 0;
154 * Check if only one FLASH bank is available
156 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
157 mtebc(PB1CR, 0); /* disable cs */
159 mtebc(PB2CR, 0); /* disable cs */
161 mtebc(PB3CR, 0); /* disable cs */
168 /*************************************************************************
169 * Override weak is_pci_host()
171 * This routine is called to determine if a pci scan should be
172 * performed. With various hardware environments (especially cPCI and
173 * PPMC) it's insufficient to depend on the state of the arbiter enable
174 * bit in the strap register, or generic host/adapter assumptions.
176 * Rather than hard-code a bad assumption in the general 440 code, the
177 * 440 pci code requires the board to decide at runtime.
179 * Return 0 for adapter mode, non-zero for host (monarch) mode.
182 ************************************************************************/
183 #if defined(CONFIG_PCI)
184 int is_pci_host(struct pci_controller *hose)
187 wait_for_pci_ready();
188 return 1; /* return 1 for host controller */
190 return 0; /* return 0 for adapter controller */
193 #endif /* defined(CONFIG_PCI) */