3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #if defined(CONFIG_CMD_NAND)
30 struct pdnb3_ndfc_regs {
39 static struct pdnb3_ndfc_regs *pdnb3_ndfc;
41 #define readb(addr) *(volatile u_char *)(addr)
42 #define readl(addr) *(volatile u_long *)(addr)
43 #define writeb(d,addr) *(volatile u_char *)(addr) = (d)
46 * The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to
47 * the NAND devices. The NDFC has command, address and data registers that
48 * when accessed will set up the NAND flash pins appropriately. We'll use the
49 * hwcontrol function to save the configuration in a global variable.
50 * We can then use this information in the read and write functions to
51 * determine which NDFC register to access.
53 * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
55 static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
57 struct nand_chip *this = mtd->priv;
59 if (ctrl & NAND_CTRL_CHANGE) {
60 if ( ctrl & NAND_CLE )
64 if ( ctrl & NAND_ALE )
68 if ( (ctrl & NAND_NCE) != NAND_NCE)
69 writeb(0x00, &(pdnb3_ndfc->term));
71 if (cmd != NAND_CMD_NONE)
72 writeb(cmd, this->IO_ADDR_W);
76 static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
78 return readb(&(pdnb3_ndfc->data));
81 static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
85 for (i = 0; i < len; i++) {
87 writeb(buf[i], &(pdnb3_ndfc->cmd));
89 writeb(buf[i], &(pdnb3_ndfc->addr));
91 writeb(buf[i], &(pdnb3_ndfc->data));
95 static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
100 for (i = 0; i < len; i++)
101 buf[i] = readb(&(pdnb3_ndfc->data));
103 ulong *ptr = (ulong *)buf;
104 int count = len >> 2;
106 for (i = 0; i < count; i++)
107 *ptr++ = readl(&(pdnb3_ndfc->data));
111 static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
115 for (i = 0; i < len; i++)
116 if (buf[i] != readb(&(pdnb3_ndfc->data)))
122 static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
127 * Blocking read to wait for NAND to be ready
129 val = readb(&(pdnb3_ndfc->wait));
137 int board_nand_init(struct nand_chip *nand)
139 pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
141 nand->ecc.mode = NAND_ECC_SOFT;
143 /* Set address of NAND IO lines (Using Linear Data Access Region) */
144 nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
145 nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
146 /* Reference hardware control function */
147 nand->cmd_ctrl = pdnb3_nand_hwcontrol;
148 nand->read_byte = pdnb3_nand_read_byte;
149 nand->write_buf = pdnb3_nand_write_buf;
150 nand->read_buf = pdnb3_nand_read_buf;
151 nand->verify_buf = pdnb3_nand_verify_buf;
152 nand->dev_ready = pdnb3_nand_dev_ready;