1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2008 Renesas Solutions Corp.
4 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
10 #include <asm/processor.h>
12 /* PRI control register */
13 #define PRPRICR5 0xFF800048 /* LMB */
14 #define PRPRICR5_D 0x2a
17 #define FPGA_NAND_CTL 0xB410020C
18 #define FPGA_NAND_RST 0x0008
19 #define FPGA_NAND_INIT 0x0000
20 #define FPGA_NAND_RST_WAIT 10000
47 /* Pin Function Controler data */
48 #define PSELA_D 0x1410
49 #define PSELB_D 0x0140
50 #define PSELC_D 0x0000
51 #define PSELD_D 0x0400
53 /* I/O Buffer Hi-Z data */
54 #define HIZCRA_D 0x0000
55 #define HIZCRB_D 0x1000
56 #define HIZCRC_D 0x0000
57 #define HIZCRD_D 0x0000
59 /* Module select reg data */
60 #define MSELCRA_D 0x0014
61 #define MSELCRB_D 0x0018
63 /* Module Stop reg Data */
64 #define MSTPCR2_D 0xFFD9F280
67 extern void init_cpld(void);
71 puts("BOARD: AP325RXA\n");
77 /* Pin Function Controler Init */
83 /* I/O Buffer Hi-Z Init */
84 outw(HIZCRA_D, HIZCRA);
85 outw(HIZCRB_D, HIZCRB);
86 outw(HIZCRC_D, HIZCRC);
87 outw(HIZCRD_D, HIZCRD);
89 /* Module select reg Init */
90 outw(MSELCRA_D, MSELCRA);
91 outw(MSELCRB_D, MSELCRB);
93 /* Module Stop reg Init */
94 outl(MSTPCR2_D, MSTPCR2);
121 /* PRI control register Init */
122 outl(PRPRICR5_D, PRPRICR5);
130 void led_set_state(unsigned short value)
134 void ide_set_reset(int idereset)
136 outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */
137 udelay(FPGA_NAND_RST_WAIT);
138 outw(FPGA_NAND_INIT, FPGA_NAND_CTL);
141 int board_eth_init(bd_t *bis)
144 #ifdef CONFIG_SMC911X
145 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);